* [PATCH 01/12] arm64: dts: renesas: Add Si-Linux CAT874 board support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 02/12] arm64: dts: renesas: Add Si-Linux EK874 " Simon Horman
` (11 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Biju Das, Fabrizio Castro, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
Basic support for the Si-Linux board based on RZ/G2E:
- Memory,
- Main crystal,
- Serial console
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/Makefile | 1 +
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 37 +++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index a8ce6594342d..11997d752e57 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
new file mode 100644
index 000000000000..6eababc93275
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a774c0.dtsi"
+
+/ {
+ model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
+ compatible = "si-linux,cat874", "renesas,r8a774c0";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <48000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 02/12] arm64: dts: renesas: Add Si-Linux EK874 board support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
2019-02-08 11:13 ` [PATCH 01/12] arm64: dts: renesas: Add Si-Linux CAT874 board support Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 03/12] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2 Simon Horman
` (10 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Biju Das, Fabrizio Castro, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
The EK874 development kit from Silicon Linux is made of CAT874 (the main
board) and CAT875 (the sub board that goes on top of CAT874).
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +-
arch/arm64/boot/dts/renesas/cat875.dtsi | 10 ++++++++++
arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts | 14 ++++++++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/renesas/cat875.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 11997d752e57..6cde526547e4 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb
+dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
new file mode 100644
index 000000000000..a41d0d81f649
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+/ {
+ model = "Silicon Linux sub board for CAT874 (CAT875)";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
new file mode 100644
index 000000000000..e7b6619ab224
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ */
+
+#include "r8a774c0-cat874.dts"
+#include "cat875.dtsi"
+
+/ {
+ model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";
+ compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 03/12] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
2019-02-08 11:13 ` [PATCH 01/12] arm64: dts: renesas: Add Si-Linux CAT874 board support Simon Horman
2019-02-08 11:13 ` [PATCH 02/12] arm64: dts: renesas: Add Si-Linux EK874 " Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 04/12] arm64: dts: renesas: r8a774c0-cat874: Add uSD support Simon Horman
` (9 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch adds pincontrol support to scif2.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 6eababc93275..c545ce5320c7 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -32,6 +32,16 @@
clock-frequency = <48000000>;
};
+&pfc {
+ scif2_pins: scif2 {
+ groups = "scif2_data_a";
+ function = "scif2";
+ };
+};
+
&scif2 {
+ pinctrl-0 = <&scif2_pins>;
+ pinctrl-names = "default";
+
status = "okay";
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/12] arm64: dts: renesas: r8a774c0-cat874: Add uSD support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (2 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 03/12] arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2 Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 05/12] arm64: dts: renesas: cat875: Add ethernet support Simon Horman
` (8 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch adds uSD card support.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 50 +++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index c545ce5320c7..477a56b3273c 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a774c0.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
@@ -26,6 +27,29 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
};
&extal_clk {
@@ -37,6 +61,18 @@
groups = "scif2_data_a";
function = "scif2";
};
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
};
&scif2 {
@@ -45,3 +81,17 @@
status = "okay";
};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 05/12] arm64: dts: renesas: cat875: Add ethernet support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (3 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 04/12] arm64: dts: renesas: r8a774c0-cat874: Add uSD support Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 06/12] arm64: dts: renesas: enable HS400 on R-Car Gen3 Simon Horman
` (7 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Biju Das, Fabrizio Castro, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch adds ethernet support to the sub board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/cat875.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index a41d0d81f649..805ffa7fb67b 100644
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -7,4 +7,34 @@
/ {
model = "Silicon Linux sub board for CAT874 (CAT875)";
+
+ aliases {
+ ethernet0 = &avb;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii";
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pfc {
+ avb_pins: avb {
+ mux {
+ groups = "avb_mii";
+ function = "avb";
+ };
+ };
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/12] arm64: dts: renesas: enable HS400 on R-Car Gen3
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (4 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 05/12] arm64: dts: renesas: cat875: Add ethernet support Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 07/12] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices Simon Horman
` (6 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Niklas Söderlund, Simon Horman
From: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Successfully tested on H3 ES2.0 and M3-N ES1.0.
Transfer rates where >160MB/s for H3 and >200MB/s for M3-N.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 +
arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index f66d990b92f1..a225c2457274 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -764,6 +764,7 @@
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index a3878fb3c3f1..e70e1bac2be4 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -463,6 +463,7 @@
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
non-removable;
status = "okay";
};
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 07/12] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (5 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 06/12] arm64: dts: renesas: enable HS400 on R-Car Gen3 Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 08/12] arm64: dts: renesas: r8a774c0: " Simon Horman
` (5 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Takeshi Kihara, Yoshihiro Kaneko,
Simon Horman
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch define OOP tables for all CPUs.
This allows CPUFreq to function.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 786178cf1ffd..b42b9c760908 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -55,6 +55,27 @@
clock-frequency = <0>;
};
+ cluster1_opp: opp_table10 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -66,6 +87,8 @@
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@1 {
@@ -75,6 +98,8 @@
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA53: cache-controller-0 {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (6 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 07/12] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 12:52 ` Sergei Shtylyov
2019-02-08 11:13 ` [PATCH 09/12] arm64: dts: renesas: r8a774c0: Add CMT device nodes Simon Horman
` (4 subsequent siblings)
12 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Fabrizio Castro, Simon Horman
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
This patch defines OOP tables for all CPUs, similarly to
what done by Takeshi Kihara and Yoshihiro Kaneko for the
R8A77990.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index f2e390f7f1d5..71ff43e3bb41 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -44,6 +44,27 @@
clock-frequency = <0>;
};
+ cluster1_opp: opp_table10 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <820000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -55,6 +76,8 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
a53_1: cpu@1 {
@@ -64,6 +87,8 @@
power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
+ operating-points-v2 = <&cluster1_opp>;
};
L2_CA53: cache-controller-0 {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
2019-02-08 11:13 ` [PATCH 08/12] arm64: dts: renesas: r8a774c0: " Simon Horman
@ 2019-02-08 12:52 ` Sergei Shtylyov
2019-02-08 15:26 ` Fabrizio Castro
0 siblings, 1 reply; 18+ messages in thread
From: Sergei Shtylyov @ 2019-02-08 12:52 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc
Cc: linux-arm-kernel, Magnus Damm, Fabrizio Castro
Hello!
On 02/08/2019 02:13 PM, Simon Horman wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> This patch defines OOP tables for all CPUs, similarly to
> what done by Takeshi Kihara and Yoshihiro Kaneko for the
> R8A77990.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
[...]
> @@ -55,6 +76,8 @@
> power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
Need space after =...
> + operating-points-v2 = <&cluster1_opp>;
> };
>
> a53_1: cpu@1 {
> @@ -64,6 +87,8 @@
> power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
> next-level-cache = <&L2_CA53>;
> enable-method = "psci";
> + clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
Here as well...
> + operating-points-v2 = <&cluster1_opp>;
> };
>
> L2_CA53: cache-controller-0 {
MBR, Sergei
^ permalink raw reply [flat|nested] 18+ messages in thread* RE: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
2019-02-08 12:52 ` Sergei Shtylyov
@ 2019-02-08 15:26 ` Fabrizio Castro
2019-02-11 9:49 ` Simon Horman
0 siblings, 1 reply; 18+ messages in thread
From: Fabrizio Castro @ 2019-02-08 15:26 UTC (permalink / raw)
To: Sergei Shtylyov, Simon Horman
Cc: linux-arm-kernel, Magnus Damm, linux-renesas-soc
Hello Sergei,
Thank you for your feedback!
> -----Original Message-----
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Sent: 08 February 2019 12:53
> To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> <fabrizio.castro@bp.renesas.com>
> Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
>
> Hello!
>
> On 02/08/2019 02:13 PM, Simon Horman wrote:
>
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > This patch defines OOP tables for all CPUs, similarly to
> > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > R8A77990.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> [...]
> > @@ -55,6 +76,8 @@
> > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
> Need space after =...
Doh! Simon, do you want me to send another version to fix both spacing issues?
Thanks,
Fab
>
> > +operating-points-v2 = <&cluster1_opp>;
> > };
> >
> > a53_1: cpu@1 {
> > @@ -64,6 +87,8 @@
> > power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;
> > next-level-cache = <&L2_CA53>;
> > enable-method = "psci";
> > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
>
>
> Here as well...
>
> > +operating-points-v2 = <&cluster1_opp>;
> > };
> >
> > L2_CA53: cache-controller-0 {
>
> MBR, Sergei
Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
2019-02-08 15:26 ` Fabrizio Castro
@ 2019-02-11 9:49 ` Simon Horman
2019-02-14 12:57 ` Fabrizio Castro
0 siblings, 1 reply; 18+ messages in thread
From: Simon Horman @ 2019-02-11 9:49 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Sergei Shtylyov, linux-arm-kernel, Magnus Damm, linux-renesas-soc
On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote:
> Hello Sergei,
>
> Thank you for your feedback!
>
> > -----Original Message-----
> > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Sent: 08 February 2019 12:53
> > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> > <fabrizio.castro@bp.renesas.com>
> > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
> >
> > Hello!
> >
> > On 02/08/2019 02:13 PM, Simon Horman wrote:
> >
> > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > >
> > > This patch defines OOP tables for all CPUs, similarly to
> > > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > > R8A77990.
> > >
> > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > [...]
> > > @@ -55,6 +76,8 @@
> > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > > next-level-cache = <&L2_CA53>;
> > > enable-method = "psci";
> > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
> >
> > Need space after =...
>
> Doh! Simon, do you want me to send another version to fix both spacing issues?
Likewise, sorry I didn't notice that earlier.
I'd rather not re-send this pull request just to resolve whitespace issues.
So please send an incremental patch for now.
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
2019-02-11 9:49 ` Simon Horman
@ 2019-02-14 12:57 ` Fabrizio Castro
0 siblings, 0 replies; 18+ messages in thread
From: Fabrizio Castro @ 2019-02-14 12:57 UTC (permalink / raw)
To: Simon Horman
Cc: Sergei Shtylyov, linux-arm-kernel, Magnus Damm, linux-renesas-soc
Hello Simon,
> From: Simon Horman <horms@verge.net.au>
> Sent: 11 February 2019 09:50
> Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
>
> On Fri, Feb 08, 2019 at 03:26:49PM +0000, Fabrizio Castro wrote:
> > Hello Sergei,
> >
> > Thank you for your feedback!
> >
> > > -----Original Message-----
> > > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > > Sent: 08 February 2019 12:53
> > > To: Simon Horman <horms+renesas@verge.net.au>; linux-renesas-soc@vger.kernel.org
> > > Cc: linux-arm-kernel@lists.infradead.org; Magnus Damm <magnus.damm@gmail.com>; Fabrizio Castro
> > > <fabrizio.castro@bp.renesas.com>
> > > Subject: Re: [PATCH 08/12] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
> > >
> > > Hello!
> > >
> > > On 02/08/2019 02:13 PM, Simon Horman wrote:
> > >
> > > > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > >
> > > > This patch defines OOP tables for all CPUs, similarly to
> > > > what done by Takeshi Kihara and Yoshihiro Kaneko for the
> > > > R8A77990.
> > > >
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > > [...]
> > > > @@ -55,6 +76,8 @@
> > > > power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;
> > > > next-level-cache = <&L2_CA53>;
> > > > enable-method = "psci";
> > > > +clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;
> > >
> > > Need space after =...
> >
> > Doh! Simon, do you want me to send another version to fix both spacing issues?
>
> Likewise, sorry I didn't notice that earlier.
>
> I'd rather not re-send this pull request just to resolve whitespace issues.
> So please send an incremental patch for now.
Thanks, will do.
Cheers,
Fab
Renesas Electronics Europe GmbH,Geschaeftsfuehrer/President : Michael Hannawald, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany,Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 09/12] arm64: dts: renesas: r8a774c0: Add CMT device nodes
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (7 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 08/12] arm64: dts: renesas: r8a774c0: " Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 10/12] arm64: dts: renesas: r8a774c0: Add TMU " Simon Horman
` (3 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch adds CMT{0|1|2|3} device nodes for r8a774c0 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 70 +++++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 71ff43e3bb41..756f960de519 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -259,6 +259,76 @@
reg = <0 0xe6060000 0 0x508>;
};
+ cmt0: timer@e60f0000 {
+ compatible = "renesas,r8a774c0-cmt0",
+ "renesas,rcar-gen3-cmt0";
+ reg = <0 0xe60f0000 0 0x1004>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 303>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 303>;
+ status = "disabled";
+ };
+
+ cmt1: timer@e6130000 {
+ compatible = "renesas,r8a774c0-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6130000 0 0x1004>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 302>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 302>;
+ status = "disabled";
+ };
+
+ cmt2: timer@e6140000 {
+ compatible = "renesas,r8a774c0-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6140000 0 0x1004>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 301>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 301>;
+ status = "disabled";
+ };
+
+ cmt3: timer@e6148000 {
+ compatible = "renesas,r8a774c0-cmt1",
+ "renesas,rcar-gen3-cmt1";
+ reg = <0 0xe6148000 0 0x1004>;
+ interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 300>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 300>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a774c0-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/12] arm64: dts: renesas: r8a774c0: Add TMU device nodes
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (8 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 09/12] arm64: dts: renesas: r8a774c0: Add CMT device nodes Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 11/12] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Simon Horman
` (2 subsequent siblings)
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch adds TMU{0|1|2|3|4} device nodes for r8a774c0 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 65 +++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 756f960de519..61a0afb74e63 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -378,6 +378,71 @@
resets = <&cpg 407>;
};
+ tmu0: timer@e61e0000 {
+ compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
+ reg = <0 0xe61e0000 0 0x30>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 125>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 125>;
+ status = "disabled";
+ };
+
+ tmu1: timer@e6fc0000 {
+ compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
+ reg = <0 0xe6fc0000 0 0x30>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 124>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 124>;
+ status = "disabled";
+ };
+
+ tmu2: timer@e6fd0000 {
+ compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
+ reg = <0 0xe6fd0000 0 0x30>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 123>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 123>;
+ status = "disabled";
+ };
+
+ tmu3: timer@e6fe0000 {
+ compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
+ reg = <0 0xe6fe0000 0 0x30>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 122>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 122>;
+ status = "disabled";
+ };
+
+ tmu4: timer@ffc00000 {
+ compatible = "renesas,tmu-r8a774c0", "renesas,tmu";
+ reg = <0 0xffc00000 0 0x30>;
+ interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 121>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 121>;
+ status = "disabled";
+ };
+
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 11/12] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (9 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 10/12] arm64: dts: renesas: r8a774c0: Add TMU " Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-08 11:13 ` [PATCH 12/12] arm64: dts: renesas: cat875: Enable PCIe support Simon Horman
2019-02-15 14:44 ` [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Arnd Bergmann
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges
mapping for pciec0 node. Also declare pcie bus clock, since it is
generated on the CAT874 main board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 477a56b3273c..96ee0d2c6357 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -56,6 +56,15 @@
clock-frequency = <48000000>;
};
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+};
+
+&pciec0 {
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+};
+
&pfc {
scif2_pins: scif2 {
groups = "scif2_data_a";
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 12/12] arm64: dts: renesas: cat875: Enable PCIe support
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (10 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 11/12] arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support Simon Horman
@ 2019-02-08 11:13 ` Simon Horman
2019-02-15 14:44 ` [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Arnd Bergmann
12 siblings, 0 replies; 18+ messages in thread
From: Simon Horman @ 2019-02-08 11:13 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm, Biju Das, Simon Horman
From: Biju Das <biju.das@bp.renesas.com>
This patch enables PCIEC0 PCI express controller on the sub board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/cat875.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi
index 805ffa7fb67b..14db66755a89 100644
--- a/arch/arm64/boot/dts/renesas/cat875.dtsi
+++ b/arch/arm64/boot/dts/renesas/cat875.dtsi
@@ -30,6 +30,10 @@
};
};
+&pciec0 {
+ status = "okay";
+};
+
&pfc {
avb_pins: avb {
mux {
--
2.11.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
2019-02-08 11:13 [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v5.1 Simon Horman
` (11 preceding siblings ...)
2019-02-08 11:13 ` [PATCH 12/12] arm64: dts: renesas: cat875: Enable PCIe support Simon Horman
@ 2019-02-15 14:44 ` Arnd Bergmann
12 siblings, 0 replies; 18+ messages in thread
From: Arnd Bergmann @ 2019-02-15 14:44 UTC (permalink / raw)
To: Simon Horman
Cc: arm-soc, Linux-Renesas, Olof Johansson, Kevin Hilman, Linux ARM,
Magnus Damm
On Fri, Feb 8, 2019 at 12:13 PM Simon Horman <horms+renesas@verge.net.au> wrote:
> Second Round of Renesas ARM64 Based SoC DT Updates for v5.1
>
> * R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards
> - Enable HS400 support for eMMC
>
> * R-Car E3 (r7a77990) SoC
> - Add OPPs table for cpu devices
>
> * RZ/G2E (r8a774c0) SoC
> - Describe TMU, CMT, SDHI devices in DT
> - Describe pincontrol support for SCIF2 device in DT
> - Add OPPs table for cpu devices
>
> * RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board,
> and CAT874 board
> - Initial support
Pulled into arm/dt, thanks!
Arnd
^ permalink raw reply [flat|nested] 18+ messages in thread