* [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks
@ 2022-10-07 13:09 Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:09 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Hi Mike, Stephen,
This patch series adds the various SASYNCPER clocks (used by modules
that must not be affected by Spread Spectrum and/or Fractional
Multiplication), and most of its derived module clocks (serial and PWM)
on the R-Car V4H (R8A7799G0) SoC.
As the second patch is a fix, and the first patch is a dependency (also
for a related DT fix), I plan to queue the first two patches in
renesas-clk-fixes for v6.1.
I plan to queue the last three patches in renesas-clk for v6.2.
Thanks for your comments!
Geert Uytterhoeven (5):
clk: renesas: r8a779g0: Add SASYNCPER clocks
clk: renesas: r8a779g0: Fix HSCIF parent clocks
clk: renesas: r8a779g0: Add SCIF clocks
clk: renesas: r8a779g0: Add PWM clock
clk: renesas: r8a779g0: Add TPU clock
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
@ 2022-10-07 13:10 ` Geert Uytterhoeven
2022-10-09 21:20 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or
Fractional Multiplication to reduce electromagnetic interference.
Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock
sources for modules that must not be affected by Spread Spectrum and/or
Fractional Multiplication.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index ad096719fd36b55b..51491b94a057b5a7 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -47,6 +47,7 @@ enum clk_ids {
CLK_S0_VIO,
CLK_S0_VC,
CLK_S0_HSC,
+ CLK_SASYNCPER,
CLK_SV_VIP,
CLK_SV_IR,
CLK_SDSRC,
@@ -84,6 +85,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED(".s0_vio", CLK_S0_VIO, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_vc", CLK_S0_VC, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s0_hsc", CLK_S0_HSC, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".sasyncper", CLK_SASYNCPER, CLK_PLL5_DIV4, 3, 1),
DEF_FIXED(".sv_vip", CLK_SV_VIP, CLK_PLL1, 5, 1),
DEF_FIXED(".sv_ir", CLK_SV_IR, CLK_PLL1, 5, 1),
DEF_BASE(".sdsrc", CLK_SDSRC, CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
@@ -128,6 +130,9 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
DEF_FIXED("s0d4_hsc", R8A779G0_CLK_S0D4_HSC, CLK_S0_HSC, 4, 1),
DEF_FIXED("cl16m_hsc", R8A779G0_CLK_CL16M_HSC, CLK_S0_HSC, 48, 1),
DEF_FIXED("s0d2_cc", R8A779G0_CLK_S0D2_CC, CLK_S0, 2, 1),
+ DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+ DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+ DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
DEF_FIXED("svd1_ir", R8A779G0_CLK_SVD1_IR, CLK_SV_IR, 1, 1),
DEF_FIXED("svd2_ir", R8A779G0_CLK_SVD2_IR, CLK_SV_IR, 2, 1),
DEF_FIXED("svd1_vip", R8A779G0_CLK_SVD1_VIP, CLK_SV_VIP, 1, 1),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
@ 2022-10-07 13:10 ` Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
As serial communication requires a clock signal, the High Speed Serial
Communication Interfaces with FIFO (HSCIF) must be clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car V4H Hardware User's Manual rev. 0.54.
Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 51491b94a057b5a7..f1f0496f7605f554 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -158,10 +158,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
- DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
- DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
- DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
- DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
+ DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
DEF_MOD("i2c0", 518, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c1", 519, R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779G0_CLK_S0D6_PER),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
@ 2022-10-07 13:10 ` Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4H (R8A779G0) SoC.
Based on a larger patch in the BSP by Kazuya Mizuguchi.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
- Use R8A779G0_CLK_SASYNCPERD4 instead of R8A779G0_CLK_RCLK, to match
the R-Car V4H Hardware User's Manual Rev. 0.54.
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index f1f0496f7605f554..c8c143c31b2beac0 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -175,6 +175,10 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
+ DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER),
DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
` (2 preceding siblings ...)
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
@ 2022-10-07 13:10 ` Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
5 siblings, 1 reply; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add the module clock used by the PWM timers on the Renesas R-Car V4H
(R8A779G0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index c8c143c31b2beac0..1215b6f516ea40c9 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -175,6 +175,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("msi3", 621, R8A779G0_CLK_MSO),
DEF_MOD("msi4", 622, R8A779G0_CLK_MSO),
DEF_MOD("msi5", 623, R8A779G0_CLK_MSO),
+ DEF_MOD("pwm", 628, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif0", 702, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif1", 703, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("scif3", 704, R8A779G0_CLK_SASYNCPERD4),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
` (3 preceding siblings ...)
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
@ 2022-10-07 13:10 ` Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
5 siblings, 1 reply; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-07 13:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
Renesas R-Car V4H (R8A779G0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 1215b6f516ea40c9..5cc5ee1295d9fe68 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -182,6 +182,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("scif4", 705, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("sydm0", 709, R8A779G0_CLK_S0D6_PER),
DEF_MOD("sydm1", 710, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
DEF_MOD("pfc0", 915, R8A779G0_CLK_CL16M),
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
` (4 preceding siblings ...)
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
@ 2022-10-07 20:47 ` Stephen Boyd
5 siblings, 0 replies; 12+ messages in thread
From: Stephen Boyd @ 2022-10-07 20:47 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette
Cc: Yoshihiro Shimoda, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Quoting Geert Uytterhoeven (2022-10-07 06:09:59)
> Hi Mike, Stephen,
>
> This patch series adds the various SASYNCPER clocks (used by modules
> that must not be affected by Spread Spectrum and/or Fractional
> Multiplication), and most of its derived module clocks (serial and PWM)
> on the R-Car V4H (R8A7799G0) SoC.
>
> As the second patch is a fix, and the first patch is a dependency (also
> for a related DT fix), I plan to queue the first two patches in
> renesas-clk-fixes for v6.1.
> I plan to queue the last three patches in renesas-clk for v6.2.
>
> Thanks for your comments!
>
> Geert Uytterhoeven (5):
> clk: renesas: r8a779g0: Add SASYNCPER clocks
> clk: renesas: r8a779g0: Fix HSCIF parent clocks
> clk: renesas: r8a779g0: Add SCIF clocks
> clk: renesas: r8a779g0: Add PWM clock
> clk: renesas: r8a779g0: Add TPU clock
>
Thanks for the heads up
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
@ 2022-10-09 21:20 ` Wolfram Sang
2022-10-10 11:15 ` Geert Uytterhoeven
0 siblings, 1 reply; 12+ messages in thread
From: Wolfram Sang @ 2022-10-09 21:20 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda, linux-clk,
linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 933 bytes --]
Hi Geert,
> + DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
> + DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
> + DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
Some spaces missing after the commas.
But my main issue is that we have it a little different for S4-8:
112 DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
113 DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
114 DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
So, no CLK_SASYNCPER at all because R8A779G0_CLK_SASYNCPERD1 divides
PLL5 directly. I don't mind which version we use but I think it should
be consistent because the diagram looks the same in the specs. What do
you think?
I'll have a look at your other patches tomorrow.
Thanks and happy hacking,
Wolfram
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
@ 2022-10-10 7:46 ` Wolfram Sang
0 siblings, 0 replies; 12+ messages in thread
From: Wolfram Sang @ 2022-10-10 7:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda, linux-clk,
linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 293 bytes --]
On Fri, Oct 07, 2022 at 03:10:03PM +0200, Geert Uytterhoeven wrote:
> Add the module clock used by the PWM timers on the Renesas R-Car V4H
> (R8A779G0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
@ 2022-10-10 7:46 ` Wolfram Sang
0 siblings, 0 replies; 12+ messages in thread
From: Wolfram Sang @ 2022-10-10 7:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda, linux-clk,
linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 312 bytes --]
On Fri, Oct 07, 2022 at 03:10:04PM +0200, Geert Uytterhoeven wrote:
> Add the module clock used by the 16-Bit Timer Pulse Unit (TPU) on the
> Renesas R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks
2022-10-09 21:20 ` Wolfram Sang
@ 2022-10-10 11:15 ` Geert Uytterhoeven
2022-10-10 18:34 ` Wolfram Sang
0 siblings, 1 reply; 12+ messages in thread
From: Geert Uytterhoeven @ 2022-10-10 11:15 UTC (permalink / raw)
To: Wolfram Sang, Michael Turquette, Stephen Boyd, Yoshihiro Shimoda,
linux-clk, linux-renesas-soc
Hi Wolfram,
On Sun, Oct 9, 2022 at 11:20 PM Wolfram Sang <wsa@kernel.org> wrote:
> > + DEF_FIXED("sasyncperd1",R8A779G0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
> > + DEF_FIXED("sasyncperd2",R8A779G0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
> > + DEF_FIXED("sasyncperd4",R8A779G0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
>
> Some spaces missing after the commas.
I did it this way to keep the columns a little bit more aligned.
The alternative is to widen the columns, and adds TABs in all rows...
> But my main issue is that we have it a little different for S4-8:
>
> 112 DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
> 113 DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
> 114 DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
>
> So, no CLK_SASYNCPER at all because R8A779G0_CLK_SASYNCPERD1 divides
> PLL5 directly. I don't mind which version we use but I think it should
> be consistent because the diagram looks the same in the specs. What do
> you think?
I can add an internal SASYNCPER clock on R-Car S4-8, too.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks
2022-10-10 11:15 ` Geert Uytterhoeven
@ 2022-10-10 18:34 ` Wolfram Sang
0 siblings, 0 replies; 12+ messages in thread
From: Wolfram Sang @ 2022-10-10 18:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Yoshihiro Shimoda, linux-clk,
linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 535 bytes --]
> > Some spaces missing after the commas.
>
> I did it this way to keep the columns a little bit more aligned.
> The alternative is to widen the columns, and adds TABs in all rows...
I see.
> > So, no CLK_SASYNCPER at all because R8A779G0_CLK_SASYNCPERD1 divides
> > PLL5 directly. I don't mind which version we use but I think it should
> > be consistent because the diagram looks the same in the specs. What do
> > you think?
>
> I can add an internal SASYNCPER clock on R-Car S4-8, too.
That would be great!
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^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-10-10 18:34 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-07 13:09 [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 1/5] clk: renesas: r8a779g0: Add SASYNCPER clocks Geert Uytterhoeven
2022-10-09 21:20 ` Wolfram Sang
2022-10-10 11:15 ` Geert Uytterhoeven
2022-10-10 18:34 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 2/5] clk: renesas: r8a779g0: Fix HSCIF parent clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 3/5] clk: renesas: r8a779g0: Add SCIF clocks Geert Uytterhoeven
2022-10-07 13:10 ` [PATCH 4/5] clk: renesas: r8a779g0: Add PWM clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 13:10 ` [PATCH 5/5] clk: renesas: r8a779g0: Add TPU clock Geert Uytterhoeven
2022-10-10 7:46 ` Wolfram Sang
2022-10-07 20:47 ` [PATCH 0/5] clk: renesas: r8a779g0: Add SASYNCPER and derived clocks Stephen Boyd
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