[PATCH 0/5] arm64: dts: renesas: r8a779g0: CPU topology improvements

[PATCH 0/5] arm64: dts: renesas: r8a779g0: CPU topology improvements

[Geert Uytterhoeven]

        Hi all,

Currently, the R-Car V4H DTS describes a single Cortex-A76 CPU core
only.  This patch series completes the description of the Cortex-A76
clusters by describing L3 caches, CPU cores 1-3, CPU map, PSCI for CPU
bring up, CPUIdle, CPU core clocks, and CPU core operating points.

This has been tested on the White-Hawk development board, where now all
4 Cortex-A76 CPU cores are available after boot.  All but the first CPU
core can be controlled from sysfs (/sys/*/*/cpu/cpu[0-3]/online).
CPU core performance follows the CPU core clocks, when changing the
frequency of the latter.

I plan to queue this in renesas-devel for v6.2.

Thanks for your comments!

Geert Uytterhoeven (5):
  arm64: dts: renesas: r8a779g0: Add L3 cache controller
  arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
  arm64: dts: renesas: r8a779g0: Add CPUIdle support
  arm64: dts: renesas: r8a779g0: Add CPU core clocks
  arm64: dts: renesas: r8a779g0: Add CA76 operating points

 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 130 +++++++++++++++++++++-
 1 file changed, 125 insertions(+), 5 deletions(-)

-- 
2.25.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH 1/5] arm64: dts: renesas: r8a779g0: Add L3 cache controller

[Geert Uytterhoeven]

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 0ea48fa18df30b6e..ef75e2603f5ac9d9 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -23,6 +23,14 @@ a76_0: cpu@0 {
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+			next-level-cache = <&L3_CA76_0>;
+		};
+
+		L3_CA76_0: cache-controller-0 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779G0_PD_A2E0D0>;
+			cache-unified;
+			cache-level = <3>;
 		};
 	};
 
-- 
2.25.1

[PATCH 2/5] arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores

[Geert Uytterhoeven]

Complete the description of the Cortex-A76 CPU cores and L3 cache
controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU
topology and PSCI support for enabling CPU cores.

R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters.

Based on a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Move device_type and enable-method properties,
  - Fix PSCI compatible value for PSCI v1.0,
  - Drop "arm,armv8" compatible values.
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 70 +++++++++++++++++++++--
 1 file changed, 65 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index ef75e2603f5ac9d9..dc5f27c114a7ad96 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -18,12 +18,60 @@ cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&a76_0>;
+				};
+				core1 {
+					cpu = <&a76_1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&a76_2>;
+				};
+				core1 {
+					cpu = <&a76_3>;
+				};
+			};
+		};
+
 		a76_0: cpu@0 {
 			compatible = "arm,cortex-a76";
 			reg = <0>;
 			device_type = "cpu";
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76_0>;
+			enable-method = "psci";
+		};
+
+		a76_1: cpu@100 {
+			compatible = "arm,cortex-a76";
+			reg = <0x100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
+			next-level-cache = <&L3_CA76_0>;
+			enable-method = "psci";
+		};
+
+		a76_2: cpu@10000 {
+			compatible = "arm,cortex-a76";
+			reg = <0x10000>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
+			next-level-cache = <&L3_CA76_1>;
+			enable-method = "psci";
+		};
+
+		a76_3: cpu@10100 {
+			compatible = "arm,cortex-a76";
+			reg = <0x10100>;
+			device_type = "cpu";
+			power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
+			next-level-cache = <&L3_CA76_1>;
+			enable-method = "psci";
 		};
 
 		L3_CA76_0: cache-controller-0 {
@@ -32,6 +80,18 @@ L3_CA76_0: cache-controller-0 {
 			cache-unified;
 			cache-level = <3>;
 		};
+
+		L3_CA76_1: cache-controller-1 {
+			compatible = "cache";
+			power-domains = <&sysc R8A779G0_PD_A2E0D1>;
+			cache-unified;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
 	};
 
 	extal_clk: extal {
@@ -1088,7 +1148,7 @@ gic: interrupt-controller@f1000000 {
 			reg = <0x0 0xf1000000 0 0x20000>,
 			      <0x0 0xf1060000 0 0x110000>;
 			interrupts = <GIC_PPI 9
-				      (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+				      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
 		prr: chipid@fff00044 {
@@ -1099,9 +1159,9 @@ prr: chipid@fff00044 {
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 };
-- 
2.25.1

[PATCH 3/5] arm64: dts: renesas: r8a779g0: Add CPUIdle support

[Geert Uytterhoeven]

Support CPUIdle for ARM Cortex-A76 on R-Car V4H.

Based on patches in the BSP by Tho Vu and Vincent Bryce.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index dc5f27c114a7ad96..21baa4936b4fba3e 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -45,6 +45,7 @@ a76_0: cpu@0 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_1: cpu@100 {
@@ -54,6 +55,7 @@ a76_1: cpu@100 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_2: cpu@10000 {
@@ -63,6 +65,7 @@ a76_2: cpu@10000 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
 		a76_3: cpu@10100 {
@@ -72,8 +75,22 @@ a76_3: cpu@10100 {
 			power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 		};
 
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+	       };
+
 		L3_CA76_0: cache-controller-0 {
 			compatible = "cache";
 			power-domains = <&sysc R8A779G0_PD_A2E0D0>;
-- 
2.25.1

[PATCH 4/5] arm64: dts: renesas: r8a779g0: Add CPU core clocks

[Geert Uytterhoeven]

Describe the clocks for the four Cortex-A76 CPU cores.
CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 21baa4936b4fba3e..9cbe337220ed4dfc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -46,6 +46,7 @@ a76_0: cpu@0 {
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_1: cpu@100 {
@@ -56,6 +57,7 @@ a76_1: cpu@100 {
 			next-level-cache = <&L3_CA76_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_2: cpu@10000 {
@@ -66,6 +68,7 @@ a76_2: cpu@10000 {
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		a76_3: cpu@10100 {
@@ -76,6 +79,7 @@ a76_3: cpu@10100 {
 			next-level-cache = <&L3_CA76_1>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
 		};
 
 		idle-states {
-- 
2.25.1

[PATCH 5/5] arm64: dts: renesas: r8a779g0: Add CA76 operating points

[Geert Uytterhoeven]

Add operating points for running the Cortex-A76 CPU cores on R-Car V4H
at various speeds, up to the Normal (1.7 GHz) performance mode.

Based on a patch in the BSP by Tho Vu.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
An operating point for the High Performance mode (1.8 GHz) is not added,
as it is not yet supported by the clock driver, and thus was not tested.
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 +++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 9cbe337220ed4dfc..45d8d927ad2642f3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -14,6 +14,33 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+		};
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+		};
+		opp-1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+		};
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <825000>;
+			clock-latency-ns = <500000>;
+			opp-suspend;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -47,6 +74,7 @@ a76_0: cpu@0 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_1: cpu@100 {
@@ -58,6 +86,7 @@ a76_1: cpu@100 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_2: cpu@10000 {
@@ -69,6 +98,7 @@ a76_2: cpu@10000 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		a76_3: cpu@10100 {
@@ -80,6 +110,7 @@ a76_3: cpu@10100 {
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
+			operating-points-v2 = <&cluster0_opp>;
 		};
 
 		idle-states {
-- 
2.25.1