* [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements
@ 2023-03-08 10:42 Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 1/8] pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume Geert Uytterhoeven
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Hi all,
This patch series contains various improvements related to power-source
handling in the Renesas R-Car pin control drivers:
- Retain I/O voltage level configuration across s2ram on R-Car D3,
- Add support for 1.8V/2.5V I/O voltage levels,
- Add support for I/O voltage level configuration for the EtherAVB,
Gigabit Ethernet, and Ethernet TSN I/O pins on R-Car V3M, V3H, E3,
D3, and V4H.
As I/O voltage level configuration is not something you want to change
without consideration, I tested this by verifying that adding e.g.
{
pins = "PIN_VDDQ_AVB0";
power-source = <2500>;
};
to the PFC node in DT triggers the right code paths.
As usual, I plan to queue these in renesas-pinctrl-for-v6.4.
Thanks for your comments!
Geert Uytterhoeven (8):
pinctrl: renesas: r8a77995: Retain POCCTRL0 register across
suspend/resume
pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag
pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
pinctrl: renesas: r8a77970: Add support for AVB power-source
pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources
pinctrl: renesas: r8a77990: Add support for AVB power-source
pinctrl: renesas: r8a77995: Add support for AVB power-source
pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources
drivers/pinctrl/renesas/core.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77470.c | 44 +++++++++++------------
drivers/pinctrl/renesas/pfc-r8a7790.c | 2 +-
drivers/pinctrl/renesas/pfc-r8a7791.c | 2 +-
drivers/pinctrl/renesas/pfc-r8a7794.c | 48 +++++++++++++-------------
drivers/pinctrl/renesas/pfc-r8a77951.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a7796.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77965.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77970.c | 34 ++++++++++++------
drivers/pinctrl/renesas/pfc-r8a77980.c | 45 ++++++++++++++++--------
drivers/pinctrl/renesas/pfc-r8a77990.c | 33 +++++++++++-------
drivers/pinctrl/renesas/pfc-r8a77995.c | 44 ++++++++++++++---------
drivers/pinctrl/renesas/pfc-r8a779g0.c | 45 +++++++++++++++++++-----
drivers/pinctrl/renesas/pinctrl.c | 22 ++++++------
drivers/pinctrl/renesas/sh_pfc.h | 13 +++----
15 files changed, 211 insertions(+), 137 deletions(-)
--
2.34.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/8] pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 2/8] pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag Geert Uytterhoeven
` (6 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
The POC Control Register 0 (POCCTRL0) on R-Car D3 is not registered in
the pinmux_ioctrl_regs[] array. Hence it is not saved/restored during
suspend/resume, and its contents may be lost after s2ram.
This went unnoticed when improving suspend/resume support in commit
d92ee9cf8ec8d7fe ("pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register
across suspend/resume").
Fix this by moving the pinmux_ioctrl_regs[] array up, and adding the
POCCTRL0 register.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index d949ae59c757924d..8e4ba9c61234bc7d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -2855,11 +2855,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
+enum ioctrl_regs {
+ POCCTRL0,
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL0] = { 0xe6060380, },
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ },
+};
+
+
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = -EINVAL;
- *pocctrl = 0xe6060380;
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
bit = 29 - (pin - RCAR_GP_PIN(3, 0));
@@ -3075,15 +3087,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
{ /* sentinel */ }
};
-enum ioctrl_regs {
- TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
-};
-
static const struct pinmux_bias_reg *
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *puen_bit, unsigned int *pud_bit)
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/8] pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 1/8] pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Geert Uytterhoeven
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Commit 537db25ca330dce0 ("pinctrl: renesas: Add I/O voltage level
flag") introduced new flags to support pins that can switch their
voltage levels between either 1.8V and 3.3V, or between 2.5V and 3.3V.
The old SH_PFC_PIN_CFG_IO_VOLTAGE flag was retained to avoid having to
change existing drivers.
Replace SH_PFC_PIN_CFG_IO_VOLTAGE by SH_PFC_PIN_CFG_IO_VOLTAGE_18_33, to
make the voltage configuration explicit, and to prepare for the advent
of support for more voltage levels.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77470.c | 44 +++++++++++------------
drivers/pinctrl/renesas/pfc-r8a7790.c | 2 +-
drivers/pinctrl/renesas/pfc-r8a7791.c | 2 +-
drivers/pinctrl/renesas/pfc-r8a7794.c | 48 +++++++++++++-------------
drivers/pinctrl/renesas/pfc-r8a77951.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a7796.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77965.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77970.c | 6 ++--
drivers/pinctrl/renesas/pfc-r8a77980.c | 6 ++--
drivers/pinctrl/renesas/pfc-r8a77990.c | 4 +--
drivers/pinctrl/renesas/pfc-r8a77995.c | 2 +-
11 files changed, 63 insertions(+), 63 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c
index b5725c3ed2b60e88..4ba710610255e580 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77470.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77470.c
@@ -13,24 +13,24 @@
#define CPU_ALL_GP(fn, sfx) \
PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -38,12 +38,12 @@
PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c
index ee21d650991bcec3..149700ee1d104ffd 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -24,7 +24,7 @@
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c
index d57458504117daa3..c83e21c4c3955814 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -22,7 +22,7 @@
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c
index 668643553a70a71a..6e801ae90d25a404 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7794.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7794.c
@@ -42,30 +42,30 @@
PORT_GP_1(5, 25, fn, sfx), \
PORT_GP_1(5, 26, fn, sfx), \
PORT_GP_1(5, 27, fn, sfx), \
- PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
- PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
+ PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c
index d4d271dff055462d..321014c8bc16f86d 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -17,12 +17,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c
index a0096ef5e68dc6d6..5db8429c54fecb02 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -22,12 +22,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c
index acd0bdf1301844ef..2b8b49b18b10b822 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -23,12 +23,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 4a7803eaafaa8abf..578c1d6fc2e0fcd9 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -19,10 +19,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index ac03309c5c0c9756..b632ea1b29c73e3a 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -19,10 +19,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx) \
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index b0936962fad709f1..57de0580a4408d4c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -22,12 +22,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 8e4ba9c61234bc7d..5a42213c680cf7b4 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -21,7 +21,7 @@
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 1/8] pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 2/8] pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-09 8:28 ` kernel test robot
2023-03-09 12:56 ` kernel test robot
2023-03-08 10:42 ` [PATCH 4/8] pinctrl: renesas: r8a77970: Add support for AVB power-source Geert Uytterhoeven
` (4 subsequent siblings)
7 siblings, 2 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Currently, the Renesas pin control driver supports pins that can switch
their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V
and 3.3V. However, some SoCs have pins that can switch between 1.8V and
2.5V.
Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE
capability and voltage level flags by a 2-bit field, to cover three
possible I/O voltage switching options.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/core.c | 4 ++--
drivers/pinctrl/renesas/pinctrl.c | 22 ++++++++++++----------
drivers/pinctrl/renesas/sh_pfc.h | 13 +++++--------
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c
index ed092ca314dd17d6..336cfae756b0f12b 100644
--- a/drivers/pinctrl/renesas/core.c
+++ b/drivers/pinctrl/renesas/core.c
@@ -1114,9 +1114,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
}
}
- if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
+ if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK) {
if (!info->ops || !info->ops->pin_to_pocctrl)
- sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
+ sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE set but .pin_to_pocctrl() not implemented\n");
else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
pin->name);
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index b7414780031990e2..f6ef658fb2276bb0 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -580,7 +580,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
case PIN_CONFIG_POWER_SOURCE:
- return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
+ return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
default:
return false;
@@ -633,7 +633,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
case PIN_CONFIG_POWER_SOURCE: {
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
- unsigned int lower_voltage;
+ unsigned int mode, lo, hi;
u32 pocctrl, val;
int bit;
@@ -646,10 +646,11 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
val = sh_pfc_read(pfc, pocctrl);
- lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
- 2500 : 1800;
+ mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
+ lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
+ hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
- arg = (val & BIT(bit)) ? 3300 : lower_voltage;
+ arg = (val & BIT(bit)) ? hi : lo;
break;
}
@@ -705,7 +706,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned int mV = pinconf_to_config_argument(configs[i]);
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
- unsigned int lower_voltage;
+ unsigned int mode, lo, hi;
u32 pocctrl, val;
int bit;
@@ -716,15 +717,16 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
- lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
- 2500 : 1800;
+ mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
+ lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
+ hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
- if (mV != lower_voltage && mV != 3300)
+ if (mV != lo && mV != hi)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
val = sh_pfc_read(pfc, pocctrl);
- if (mV == 3300)
+ if (mV == hi)
val |= BIT(bit);
else
val &= ~BIT(bit);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 83312fac14e5ddce..8dc7a66009ad842c 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -29,16 +29,13 @@ enum {
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
-#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
-#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
-#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25 (1 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (2 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (3 << 4)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
- SH_PFC_PIN_VOLTAGE_18_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
- SH_PFC_PIN_VOLTAGE_25_33)
+#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/8] pinctrl: renesas: r8a77970: Add support for AVB power-source
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
` (2 preceding siblings ...)
2023-03-08 10:42 ` [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 5/8] pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources Geert Uytterhoeven
` (3 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB
pins on the R-Car V3M SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V
or 3.3V operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77970.c | 28 ++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 578c1d6fc2e0fcd9..54da0c025458d0a7 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -34,7 +34,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -2364,19 +2365,30 @@ static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
- if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
+
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7;
- return -EINVAL;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
+
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/8] pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
` (3 preceding siblings ...)
2023-03-08 10:42 ` [PATCH 4/8] pinctrl: renesas: r8a77970: Add support for AVB power-source Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 6/8] pinctrl: renesas: r8a77990: Add support for AVB power-source Geert Uytterhoeven
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Add support for configuring the I/O voltage levels of the Ethernet AVB
and Gigabit Ethernet pins on the R-Car V3H SoC. "PIN_VDDQ_AVB" and
"PIN_VDDQ_GE" can be configured for 2.5V or 3.3V operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77980.c | 39 ++++++++++++++++++--------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index b632ea1b29c73e3a..8effbcec0b227ee3 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -35,7 +35,9 @@
PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
+ PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -2837,24 +2839,39 @@ static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit + 22;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
- if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+ case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit - 10;
- if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
- (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
+
+ case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
return bit + 7;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
- if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+ case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
return pin - 25;
- return -EINVAL;
+ case PIN_VDDQ_AVB:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+ return 0;
+
+ case PIN_VDDQ_GE:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+ return 1;
+
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/8] pinctrl: renesas: r8a77990: Add support for AVB power-source
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
` (4 preceding siblings ...)
2023-03-08 10:42 ` [PATCH 5/8] pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 7/8] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 8/8] pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources Geert Uytterhoeven
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB
pins on the R-Car E3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or
3.3V operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 29 +++++++++++++++++---------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c
index 57de0580a4408d4c..229ad12bc9b7e6b0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -56,7 +56,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -507,7 +508,8 @@ MOD_SEL0_1_0
FM(AVB_TD3) \
FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
FM(ASEBRK) \
- FM(MLB_REF)
+ FM(MLB_REF) \
+ FM(VDDQ_AVB0)
enum {
PINMUX_RESERVED = 0,
@@ -5040,28 +5042,35 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POCCTRL0,
+ POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return (pin & 0x1f) + 19;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
- bit = pin & 0x1f;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
- bit = (pin & 0x1f) + 19;
-
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/8] pinctrl: renesas: r8a77995: Add support for AVB power-source
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
` (5 preceding siblings ...)
2023-03-08 10:42 ` [PATCH 6/8] pinctrl: renesas: r8a77990: Add support for AVB power-source Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 8/8] pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources Geert Uytterhoeven
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Add support for configuring the I/O voltage level of the Ethernet AVB
pins on the R-Car D3 SoC. "PIN_VDDQ_AVB0" can be configured for 2.5V or
3.3V operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 5a42213c680cf7b4..29664d97e5ec0748 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -34,7 +34,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -2857,11 +2858,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
enum ioctrl_regs {
POCCTRL0,
+ POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
{ /* sentinel */ },
};
@@ -2869,14 +2872,18 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
-
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return 29 - (pin - RCAR_GP_PIN(3, 0));
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
- bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 8/8] pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources
2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
` (6 preceding siblings ...)
2023-03-08 10:42 ` [PATCH 7/8] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
@ 2023-03-08 10:42 ` Geert Uytterhoeven
7 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-08 10:42 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Add support for configuring the I/O voltage levels of the Ethernet AVB
and Ethernet TSN pins on the R-Car V4H SoC. "PIN_VDDQ_AVB[012]" and
"PIN_VDDQ_TSN0" can be configured for 1.8V or 2.5V operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 45 ++++++++++++++++++++------
1 file changed, 36 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index a4e4759328367726..3243668522823383 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -49,6 +49,12 @@
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
+#define CPU_ALL_NOGP(fn) \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \
+ PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25)
+
/* GPSR0 */
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
@@ -1221,10 +1227,12 @@ static const u16 pinmux_data[] = {
*/
enum {
GP_ASSIGN_LAST(),
+ NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
+ PINMUX_NOGP_ALL(),
};
/* - AUDIO CLOCK ----------------------------------------- */
@@ -4086,23 +4094,42 @@ static int r8a779g0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POC0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 18))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
+ *pocctrl = pinmux_ioctrl_regs[POC0].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC1].reg;
- if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 22))
+ case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
+ *pocctrl = pinmux_ioctrl_regs[POC1].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC3].reg;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 12))
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
+ *pocctrl = pinmux_ioctrl_regs[POC3].reg;
return bit;
- *pocctrl = pinmux_ioctrl_regs[POC8].reg;
- if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 13))
+ case PIN_VDDQ_TSN0:
+ *pocctrl = pinmux_ioctrl_regs[POC4].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB2:
+ *pocctrl = pinmux_ioctrl_regs[POC5].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB1:
+ *pocctrl = pinmux_ioctrl_regs[POC6].reg;
+ return 0;
+
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POC7].reg;
+ return 0;
+
+ case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
+ *pocctrl = pinmux_ioctrl_regs[POC8].reg;
return bit;
- return -EINVAL;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
2023-03-08 10:42 ` [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Geert Uytterhoeven
@ 2023-03-09 8:28 ` kernel test robot
2023-03-09 8:31 ` Geert Uytterhoeven
2023-03-09 12:56 ` kernel test robot
1 sibling, 1 reply; 12+ messages in thread
From: kernel test robot @ 2023-03-09 8:28 UTC (permalink / raw)
To: Geert Uytterhoeven, Linus Walleij
Cc: oe-kbuild-all, linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Hi Geert,
I love your patch! Yet something to improve:
[auto build test ERROR on geert-renesas-drivers/renesas-pinctrl]
[also build test ERROR on linusw-pinctrl/devel linusw-pinctrl/for-next linus/master v6.3-rc1 next-20230309]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
patch link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert%2Brenesas%40glider.be
patch subject: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
config: nios2-randconfig-r004-20230309 (https://download.01.org/0day-ci/archive/20230309/202303091612.UKr8Fhos-lkp@intel.com/config)
compiler: nios2-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/513932515f943c5987c5a214520f6875cd507c3e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
git checkout 513932515f943c5987c5a214520f6875cd507c3e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 SHELL=/bin/bash drivers/pinctrl/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303091612.UKr8Fhos-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/pinctrl/renesas/pfc-r8a77950.c:11:
>> drivers/pinctrl/renesas/pfc-r8a77950.c:19:48: error: 'SH_PFC_PIN_CFG_IO_VOLTAGE' undeclared here (not in a function); did you mean 'SH_PFC_PIN_CFG_IO_VOLTAGE_MASK'?
19 | PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:620:20: note: in definition of macro '_GP_GPIO'
620 | .configs = cfg, \
| ^~~
drivers/pinctrl/renesas/sh_pfc.h:447:9: note: in expansion of macro 'PORT_GP_CFG_1'
447 | PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:452:9: note: in expansion of macro 'PORT_GP_CFG_2'
452 | PORT_GP_CFG_2(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:458:9: note: in expansion of macro 'PORT_GP_CFG_4'
458 | PORT_GP_CFG_4(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:464:9: note: in expansion of macro 'PORT_GP_CFG_6'
464 | PORT_GP_CFG_6(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:469:9: note: in expansion of macro 'PORT_GP_CFG_7'
469 | PORT_GP_CFG_7(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:474:9: note: in expansion of macro 'PORT_GP_CFG_8'
474 | PORT_GP_CFG_8(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:479:9: note: in expansion of macro 'PORT_GP_CFG_9'
479 | PORT_GP_CFG_9(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:484:9: note: in expansion of macro 'PORT_GP_CFG_10'
484 | PORT_GP_CFG_10(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:489:9: note: in expansion of macro 'PORT_GP_CFG_11'
489 | PORT_GP_CFG_11(bank, fn, sfx, cfg), \
| ^~~~~~~~~~~~~~
drivers/pinctrl/renesas/pfc-r8a77950.c:19:9: note: in expansion of macro 'PORT_GP_CFG_12'
19 | PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
| ^~~~~~~~~~~~~~
drivers/pinctrl/renesas/sh_pfc.h:622:41: note: in expansion of macro 'CPU_ALL_GP'
622 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
| ^~~~~~~~~~
drivers/pinctrl/renesas/pfc-r8a77950.c:1502:9: note: in expansion of macro 'PINMUX_GPIO_GP_ALL'
1502 | PINMUX_GPIO_GP_ALL(),
| ^~~~~~~~~~~~~~~~~~
vim +19 drivers/pinctrl/renesas/pfc-r8a77950.c
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 14
bd79c92039f117 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2019-03-21 15 #define CPU_ALL_GP(fn, sfx) \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 16 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 17 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 18 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 @19 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 20 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 21 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 22 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 23 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 24 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 25 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 26 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 27 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
4f062bcb588972 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2019-01-15 28
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
2023-03-09 8:28 ` kernel test robot
@ 2023-03-09 8:31 ` Geert Uytterhoeven
0 siblings, 0 replies; 12+ messages in thread
From: Geert Uytterhoeven @ 2023-03-09 8:31 UTC (permalink / raw)
To: kernel test robot
Cc: Linus Walleij, oe-kbuild-all, linux-renesas-soc, linux-gpio
Hi Robot,
On Thu, Mar 9, 2023 at 9:29 AM kernel test robot <lkp@intel.com> wrote:
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on geert-renesas-drivers/renesas-pinctrl]
> [also build test ERROR on linusw-pinctrl/devel linusw-pinctrl/for-next linus/master v6.3-rc1 next-20230309]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
> base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
> patch link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert%2Brenesas%40glider.be
> patch subject: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
> config: nios2-randconfig-r004-20230309 (https://download.01.org/0day-ci/archive/20230309/202303091612.UKr8Fhos-lkp@intel.com/config)
> compiler: nios2-linux-gcc (GCC) 12.1.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # https://github.com/intel-lab-lkp/linux/commit/513932515f943c5987c5a214520f6875cd507c3e
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
> git checkout 513932515f943c5987c5a214520f6875cd507c3e
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 olddefconfig
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=nios2 SHELL=/bin/bash drivers/pinctrl/
>
> If you fix the issue, kindly add following tag where applicable
> | Reported-by: kernel test robot <lkp@intel.com>
> | Link: https://lore.kernel.org/oe-kbuild-all/202303091612.UKr8Fhos-lkp@intel.com/
>
> All errors (new ones prefixed by >>):
>
> In file included from drivers/pinctrl/renesas/pfc-r8a77950.c:11:
> >> drivers/pinctrl/renesas/pfc-r8a77950.c:19:48: error: 'SH_PFC_PIN_CFG_IO_VOLTAGE' undeclared here (not in a function); did you mean 'SH_PFC_PIN_CFG_IO_VOLTAGE_MASK'?
> 19 | PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
> | ^~~~~~~~~~~~~~~~~~~~~~~~~
This driver is scheduled for removal, hence was not updated.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
2023-03-08 10:42 ` [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Geert Uytterhoeven
2023-03-09 8:28 ` kernel test robot
@ 2023-03-09 12:56 ` kernel test robot
1 sibling, 0 replies; 12+ messages in thread
From: kernel test robot @ 2023-03-09 12:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Linus Walleij
Cc: llvm, oe-kbuild-all, linux-renesas-soc, linux-gpio, Geert Uytterhoeven
Hi Geert,
I love your patch! Yet something to improve:
[auto build test ERROR on geert-renesas-drivers/renesas-pinctrl]
[also build test ERROR on linusw-pinctrl/devel linusw-pinctrl/for-next linus/master v6.3-rc1 next-20230309]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl
patch link: https://lore.kernel.org/r/0c04925457bf3f7e78e7e3851528d9a4c29246da.1678271030.git.geert%2Brenesas%40glider.be
patch subject: [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
config: s390-buildonly-randconfig-r003-20230308 (https://download.01.org/0day-ci/archive/20230309/202303092028.R5gxePOb-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 67409911353323ca5edf2049ef0df54132fa1ca7)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install s390 cross compiling tool for clang build
# apt-get install binutils-s390x-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/513932515f943c5987c5a214520f6875cd507c3e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Geert-Uytterhoeven/pinctrl-renesas-r8a77995-Retain-POCCTRL0-register-across-suspend-resume/20230308-212328
git checkout 513932515f943c5987c5a214520f6875cd507c3e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=s390 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=s390 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202303092028.R5gxePOb-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
PINMUX_GPIO_GP_ALL(),
^
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:19:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
>> drivers/pinctrl/renesas/pfc-r8a77950.c:1502:2: error: use of undeclared identifier 'SH_PFC_PIN_CFG_IO_VOLTAGE'
drivers/pinctrl/renesas/sh_pfc.h:622:31: note: expanded from macro 'PINMUX_GPIO_GP_ALL'
#define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused)
^
drivers/pinctrl/renesas/pfc-r8a77950.c:24:41: note: expanded from macro 'CPU_ALL_GP'
PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
vim +/SH_PFC_PIN_CFG_IO_VOLTAGE +1502 drivers/pinctrl/renesas/pfc-r8a77950.c
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 1500
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 1501 static const struct sh_pfc_pin pinmux_pins[] = {
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 @1502 PINMUX_GPIO_GP_ALL(),
4f062bcb588972 drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2019-01-15 1503 PINMUX_NOGP_ALL(),
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 1504 };
b205914c8f822e drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c Geert Uytterhoeven 2016-10-03 1505
--
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https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-03-09 12:58 UTC | newest]
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2023-03-08 10:42 [PATCH 0/8] pinctrl: renesas: rcar: power-source improvements Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 1/8] pinctrl: renesas: r8a77995: Retain POCCTRL0 register across suspend/resume Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 2/8] pinctrl: renesas: rcar: Phase out old SH_PFC_PIN_CFG_IO_VOLTAGE flag Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 3/8] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels Geert Uytterhoeven
2023-03-09 8:28 ` kernel test robot
2023-03-09 8:31 ` Geert Uytterhoeven
2023-03-09 12:56 ` kernel test robot
2023-03-08 10:42 ` [PATCH 4/8] pinctrl: renesas: r8a77970: Add support for AVB power-source Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 5/8] pinctrl: renesas: r8a77980: Add support for AVB/GE power-sources Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 6/8] pinctrl: renesas: r8a77990: Add support for AVB power-source Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 7/8] pinctrl: renesas: r8a77995: " Geert Uytterhoeven
2023-03-08 10:42 ` [PATCH 8/8] pinctrl: renesas: r8a779g0: Add support for AVB/TSN power-sources Geert Uytterhoeven
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