Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board

[Atish Patra <Atish.Patra@wdc.com>]

On Tue, 2021-03-09 at 13:30 +0000, Lewis.Hanly@microchip.com wrote:
> 
> 
> From: Ben Dooks <ben.dooks@codethink.co.uk>
> Sent: Tuesday, March 9, 2021 10:56 AM
> To: Atish Patra <atish.patra@wdc.com>; linux-kernel@vger.kernel.org <
> linux-kernel@vger.kernel.org>
> Cc: Albert Ou <aou@eecs.berkeley.edu>; Alistair Francis <
> alistair.francis@wdc.com>; Anup Patel <anup.patel@wdc.com>; Björn
> Töpel <bjorn@kernel.org>; devicetree@vger.kernel.org <
> devicetree@vger.kernel.org>; linux-riscv@lists.infradead.org <
> linux-riscv@lists.infradead.org>; Palmer Dabbelt
> <palmer@dabbelt.com>; Paul Walmsley <paul.walmsley@sifive.com>; Rob
> Herring < robh+dt@kernel.org>; Conor Dooley - M52691 <
> Conor.Dooley@microchip.com>; Daire McNamara - X61553 <
> Daire.McNamara@microchip.com>; Ivan Griffin - X61451 <
> Ivan.Griffin@microchip.com>; Lewis Hanly - M34782 <
> Lewis.Hanly@microchip.com>
> Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE
> board 
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> On 03/03/2021 20:02, Atish Patra wrote:
> > Add initial DTS for Microchip ICICLE board having only
> > essential devices (clocks, sdhci, ethernet, serial, etc).
> > The device tree is based on the U-Boot patch.
> > 
> > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/
> > 
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> >    arch/riscv/boot/dts/Makefile                  |   1 +
> >    arch/riscv/boot/dts/microchip/Makefile        |   2 +
> >    .../microchip/microchip-mpfs-icicle-kit.dts   |  72 ++++
> >    .../boot/dts/microchip/microchip-mpfs.dtsi    | 329
> > ++++++++++++++++++
> >    4 files changed, 404 insertions(+)
> >    create mode 100644 arch/riscv/boot/dts/microchip/Makefile
> >    create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-
> > icicle-kit.dts
> >    create mode 100644 arch/riscv/boot/dts/microchip/microchip-
> > mpfs.dtsi
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile
> > b/arch/riscv/boot/dts/Makefile
> > index 7ffd502e3e7b..fe996b88319e 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> >    # SPDX-License-Identifier: GPL-2.0
> >    subdir-y += sifive
> >    subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > +subdir-y += microchip
> > 
> >    obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/microchip/Makefile
> > b/arch/riscv/boot/dts/microchip/Makefile
> > new file mode 100644
> > index 000000000000..622b12771fd3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-
> > kit.dtb
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-
> > kit.dts
> > new file mode 100644
> > index 000000000000..ec79944065c9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,72 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +
> > +#include "microchip-mpfs.dtsi"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ          1000000
> > +
> > +/ {
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +     model = "Microchip PolarFire-SoC Icicle Kit";
> > +     compatible = "microchip,mpfs-icicle-kit";
> > +
> > +     chosen {
> > +             stdout-path = &serial0;
> > +     };
> > +
> > +     cpus {
> > +             timebase-frequency = <RTCCLK_FREQ>;
> > +     };
> > +
> > +     memory@80000000 {
> > +             device_type = "memory";
> > +             reg = <0x0 0x80000000 0x0 0x40000000>;
> > +             clocks = <&clkcfg 26>;
> > +     };
> > +
> 
> The latest Microchip releases have two memory nodes to provide the
> full 2GiB of memory space.
> > > For this release we want to leave it at 1GB, wip memory remapping
> > > with the newer releases.
> 

Thanks for the clarification. For some reason, your reply did not land
in the mailing lists.


> > +     soc {
> > +     };
> > +};
> > +
> > +&serial0 {
> > +     status = "okay";
> > +};
> > +
> > +&serial1 {
> > +     status = "okay";
> > +};
> > +
> > +&serial2 {
> > +     status = "okay";
> > +};
> > +
> > +&serial3 {
> > +     status = "okay";
> > +};
> > +
> > +&sdcard {
> > +     status = "okay";
> > +};
> > +
> > +&emac0 {
> > +     phy-mode = "sgmii";
> > +     phy-handle = <&phy0>;
> > +     phy0: ethernet-phy@8 {
> > +             reg = <8>;
> > +             ti,fifo-depth = <0x01>;
> > +     };
> > +};
> > +
> > +&emac1 {
> > +     status = "okay";
> > +     phy-mode = "sgmii";
> > +     phy-handle = <&phy1>;
> > +     phy1: ethernet-phy@9 {
> > +             reg = <9>;
> > +             ti,fifo-depth = <0x01>;
> > +     };
> > +};
> 
> 
> 
> --
> Ben Dooks                               http://www.codethink.co.uk/
> Senior Engineer                         Codethink - Providing Genius
> 
> https://www.codethink.co.uk/privacy.html

-- 
Regards,
Atish
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