From: Yash Shah <yash.shah@sifive.com>
To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org
Cc: mark.rutland@arm.com, aou@eecs.berkeley.edu, palmer@sifive.com,
sachin.ghadi@sifive.com, Yash Shah <yash.shah@sifive.com>,
robh+dt@kernel.org, bp@alien8.de, paul.walmsley@sifive.com,
james.morse@arm.com, mchehab@kernel.org
Subject: [PATCH 0/3] L2 cache controller and EDAC support for SiFive SoCs
Date: Mon, 15 Apr 2019 17:10:40 +0530 [thread overview]
Message-ID: <1555328443-30874-1-git-send-email-yash.shah@sifive.com> (raw)
This patch series adds an L2 cache controller driver with DT documentation
and an EDAC platform driver for SiFive SoCs.
The EDAC platform driver registers for notifier events from the L2 cache
controller driver for L2 ECC events.
This patchset is based on Linux 5.1-rc2 and tested on HiFive Unleashed
board with additional board related patches needed for testing can be found
at dev/yashs/L2_cache_controller branch of:
https://github.com/yashshah7/riscv-linux.git
Yash Shah (3):
RISC-V: Add DT documentation for SiFive L2 Cache Controller
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive
SoCs
edac: sifive: Add EDAC platform driver for SiFive SoCs
.../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 +++++
arch/riscv/Kconfig | 1 +
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/sifive_l2_cache.c | 224 +++++++++++++++++++++
drivers/edac/Kconfig | 6 +
drivers/edac/Makefile | 1 +
drivers/edac/sifive_edac.c | 121 +++++++++++
7 files changed, 407 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
create mode 100644 arch/riscv/mm/sifive_l2_cache.c
create mode 100644 drivers/edac/sifive_edac.c
--
1.9.1
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next reply other threads:[~2019-04-15 11:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-15 11:40 Yash Shah [this message]
2019-04-15 11:40 ` [PATCH 1/3] RISC-V: Add DT documentation for SiFive L2 Cache Controller Yash Shah
2019-04-18 12:40 ` Borislav Petkov
2019-04-15 11:40 ` [PATCH 2/3] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs Yash Shah
2019-04-15 11:40 ` [PATCH 3/3] edac: sifive: Add EDAC platform " Yash Shah
2019-04-18 12:50 ` Borislav Petkov
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