From: Johan Hovold <johan@kernel.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: Rob Herring <robh@kernel.org>, Albert Ou <aou@eecs.berkeley.edu>,
Jason Cooper <jason@lakedaemon.net>,
Alan Kao <alankao@andestech.com>,
Dmitriy Cherkasov <dmitriy@oss-tech.org>,
Andreas Schwab <schwab@suse.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Johan Hovold <johan@kernel.org>,
linux-kernel@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [v4 PATCH 8/8] RISC-V: Assign hwcap as per comman capabilities.
Date: Tue, 12 Feb 2019 12:25:34 +0100 [thread overview]
Message-ID: <20190212112534.GB28278@localhost> (raw)
In-Reply-To: <1549969812-22502-9-git-send-email-atish.patra@wdc.com>
On Tue, Feb 12, 2019 at 03:10:12AM -0800, Atish Patra wrote:
> Currently, we set hwcap based on first valid hart from DT. This may not
> be correct always as that hart might not be current booting cpu or may
> have a different capability.
>
> Set hwcap as the capabilities supported by all possible harts with "okay"
> status.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++-------------------
> 1 file changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index e7a4701f..a1e4fb34 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -20,6 +20,7 @@
> #include <linux/of.h>
> #include <asm/processor.h>
> #include <asm/hwcap.h>
> +#include <asm/smp.h>
>
> unsigned long elf_hwcap __read_mostly;
> #ifdef CONFIG_FPU
> @@ -42,28 +43,30 @@ void riscv_fill_hwcap(void)
>
> elf_hwcap = 0;
>
> - /*
> - * We don't support running Linux on hertergenous ISA systems. For
> - * now, we just check the ISA of the first "okay" processor.
> - */
> for_each_of_cpu_node(node) {
> - if (riscv_of_processor_hartid(node) >= 0)
> - break;
> - }
> - if (!node) {
> - pr_warn("Unable to find \"cpu\" devicetree entry\n");
> - return;
> - }
> + unsigned long this_hwcap = 0;
>
> - if (of_property_read_string(node, "riscv,isa", &isa)) {
> - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> - of_node_put(node);
> - return;
> - }
> - of_node_put(node);
> + if (riscv_of_processor_hartid(node) < 0)
> + continue;
>
> - for (i = 0; i < strlen(isa); ++i)
> - elf_hwcap |= isa2hwcap[(unsigned char)(isa[i])];
> + if (of_property_read_string(node, "riscv,isa", &isa)) {
> + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
> + return;
Did you want "continue" here to continue processing the other harts?
Note that you currently leak the device node when returning.
Johan
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-02-12 11:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 11:10 [v4 PATCH 0/8] Various SMP related fixes Atish Patra
2019-02-12 11:10 ` [v4 PATCH 1/8] RISC-V: Do not wait indefinitely in __cpu_up Atish Patra
2019-02-12 11:10 ` [v4 PATCH 2/8] RISC-V: Move cpuid to hartid mapping to SMP Atish Patra
2019-02-12 11:10 ` [v4 PATCH 3/8] RISC-V: Remove NR_CPUs check during hartid search from DT Atish Patra
2019-02-12 11:10 ` [v4 PATCH 4/8] RISC-V: Allow hartid-to-cpuid function to fail Atish Patra
2019-02-12 11:10 ` [v4 PATCH 5/8] RISC-V: Compare cpuid with NR_CPUS before mapping Atish Patra
2019-02-12 11:10 ` [v4 PATCH 6/8] clocksource/drivers/riscv: Add required checks during clock source init Atish Patra
2019-02-13 6:43 ` Anup Patel
2019-02-13 8:48 ` Daniel Lezcano
2019-02-14 0:37 ` Palmer Dabbelt
2019-02-12 11:10 ` [v4 PATCH 7/8] irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid Atish Patra
2019-02-14 12:24 ` Marc Zyngier
2019-02-12 11:10 ` [v4 PATCH 8/8] RISC-V: Assign hwcap as per comman capabilities Atish Patra
2019-02-12 11:25 ` Johan Hovold [this message]
2019-02-12 19:58 ` Atish Patra
2019-02-13 8:44 ` Johan Hovold
2019-02-13 19:59 ` Atish Patra
2019-02-14 0:37 ` Palmer Dabbelt
2019-02-14 23:49 ` Atish Patra
2019-02-22 19:21 ` Atish Patra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190212112534.GB28278@localhost \
--to=johan@kernel.org \
--cc=alankao@andestech.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=daniel.lezcano@linaro.org \
--cc=dmitriy@oss-tech.org \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=palmer@sifive.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
--cc=schwab@suse.de \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).