From: Sudeep Holla <sudeep.holla@arm.com>
To: Yash Shah <yash.shah@sifive.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, Sudeep Holla <sudeep.holla@arm.com>,
Sachin Ghadi <sachin.ghadi@sifive.com>,
robh+dt@kernel.org, Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller
Date: Fri, 26 Apr 2019 10:34:14 +0100 [thread overview]
Message-ID: <20190426093358.GA28309@e107155-lin> (raw)
In-Reply-To: <CAJ2_jOEBqBnorz9PcQp72Jjju9RX_P8mU=Gq+0xCCcWsBiJksw@mail.gmail.com>
On Fri, Apr 26, 2019 at 11:20:17AM +0530, Yash Shah wrote:
> On Thu, Apr 25, 2019 at 3:43 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
> >
> > On Thu, Apr 25, 2019 at 11:24:55AM +0530, Yash Shah wrote:
> > > Add device tree bindings for SiFive FU540 L2 cache controller driver
> > >
> > > Signed-off-by: Yash Shah <yash.shah@sifive.com>
> > > ---
> > > .../devicetree/bindings/riscv/sifive-l2-cache.txt | 53 ++++++++++++++++++++++
> > > 1 file changed, 53 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> > > new file mode 100644
> > > index 0000000..15132e2
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> > > @@ -0,0 +1,53 @@
> > > +SiFive L2 Cache Controller
> > > +--------------------------
> > > +The SiFive Level 2 Cache Controller is used to provide access to fast copies
> > > +of memory for masters in a Core Complex. The Level 2 Cache Controller also
> > > +acts as directory-based coherency manager.
> > > +
> > > +Required Properties:
> > > +--------------------
> > > +- compatible: Should be "sifive,fu540-c000-ccache"
> > > +
> > > +- cache-block-size: Specifies the block size in bytes of the cache
> > > +
> > > +- cache-level: Should be set to 2 for a level 2 cache
> > > +
> > > +- cache-sets: Specifies the number of associativity sets of the cache
> > > +
> > > +- cache-size: Specifies the size in bytes of the cache
> > > +
> > > +- cache-unified: Specifies the cache is a unified cache
> > > +
> > > +- interrupt-parent: Must be core interrupt controller
> > > +
> > > +- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
> > > +
> > > +- reg: Physical base address and size of L2 cache controller registers map
> > > +
> > > +- reg-names: Should be "control"
> > > +
> >
> > It would be good if you mark the properties that are present in DT
> > specification and those that are added for sifive,fu540-c000-ccache
>
> I believe there isn't any property which is added explicitly for
> sifive,fu540-c000-ccache.
>
reg and interrupts are generally optional for normal cache and may be
required for cache controller like this. DT specification[1] covers
only caches and not cache controllers.
--
Regards,
Sudeep
[1] https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
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next prev parent reply other threads:[~2019-04-26 9:34 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-25 5:54 [PATCH 0/2] L2 cache controller support for SiFive FU540 Yash Shah
2019-04-25 5:54 ` [PATCH 1/2] RISC-V: Add DT documentation for SiFive L2 Cache Controller Yash Shah
2019-04-25 10:13 ` Sudeep Holla
2019-04-26 5:50 ` Yash Shah
2019-04-26 9:34 ` Sudeep Holla [this message]
2019-04-30 4:20 ` Yash Shah
2019-05-02 0:41 ` Rob Herring
2019-05-02 5:20 ` Yash Shah
2019-05-02 9:10 ` Sudeep Holla
2019-05-02 9:35 ` Yash Shah
2019-04-25 5:54 ` [PATCH 2/2] RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs Yash Shah
2019-04-25 10:17 ` Sudeep Holla
2019-04-26 5:34 ` Yash Shah
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