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From: Christoph Hellwig <hch@lst.de>
To: Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: RISC-V nommu support v4
Date: Tue,  3 Sep 2019 11:32:19 +0200	[thread overview]
Message-ID: <20190903093239.21278-1-hch@lst.de> (raw)

Hi all,

below is a series to support nommu mode on RISC-V.  For now this series
just works under qemu with the qemu-virt platform, but Damien has also
been able to get kernel based on this tree with additional driver hacks
to work on the Kendryte KD210, but that will take a while to cleanup
an upstream.

A git tree is available here:

    git://git.infradead.org/users/hch/riscv.git riscv-nommu.4

Gitweb:

    http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-nommu.4

I've also pushed out a builtroot branch that can build a RISC-V nommu
root filesystem here:

   git://git.infradead.org/users/hch/buildroot.git riscv-nommu.2

Gitweb:

   http://git.infradead.org/users/hch/buildroot.git/shortlog/refs/heads/riscv-nommu.2


Changes since v3:
 - improve a few commit message
 - cleanup riscv_cpuid_to_hartid_mask
 - cleanup the timer handling
 - cleanup the IPI handling a little more
 - renamed CONFIG_M_MODE to CONFIG_RISCV_M_MODE
 - split out CONFIG_RISCV_SBI to make some of the ifdefs more obbious
 - use IS_ENABLED wherever possible instead of if ifdefs to make the
   code more readable

Changes since v2:
 - rebased to 5.3-rc
 - remove the EFI image header for nommu builds
 - set ARCH_SLAB_MINALIGN to ensure stack alignment in the flat binary
   loader
 - minor comment improvement
 - use #defines for more CSRs

Changes since v1:
 - fixes so that a kernel with this series still work on builds with an
   IOMMU
 - small clint cleanups
 - the binfmt_flat base and buildroot now don't put arguments on the stack

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             reply	other threads:[~2019-09-03  9:32 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-03  9:32 Christoph Hellwig [this message]
2019-09-03  9:32 ` [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-09-03  9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig
2019-09-03  9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig
2019-09-03  9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig
2019-09-03  9:32 ` [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask Christoph Hellwig
2019-09-03  9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig
2019-09-03  9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig
2019-09-03  9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-10-16  2:07   ` Paul Walmsley
2019-10-17 16:20     ` Christoph Hellwig
2019-09-03  9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-09-03  9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig
2019-09-03  9:32 ` [PATCH 11/20] riscv: cleanup the default power off implementation Christoph Hellwig
2019-09-03  9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-09-03  9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-09-03  9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig
2019-09-03  9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-09-03  9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-09-03  9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-09-03  9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig
2019-09-03  9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig
2019-09-03  9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig

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