Linux-RISC-V Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
@ 2019-09-25 13:12 Rob Herring
  2019-09-25 21:24 ` Palmer Dabbelt
  0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2019-09-25 13:12 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: devicetree, linux-riscv, Palmer Dabbelt, linux-kernel, Albert Ou

Fix the errors in the RiscV CPU DT schema:

Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property

Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
v2:
 - Add timebase-frequency to simulator example.

 .../devicetree/bindings/riscv/cpus.yaml       | 26 ++++++++++---------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index b261a3015f84..eb0ef19829b6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -24,15 +24,17 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,rocket0
-          - sifive,e5
-          - sifive,e51
-          - sifive,u54-mc
-          - sifive,u54
-          - sifive,u5
-      - const: riscv
+    oneOf:
+      - items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+      - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
       and identifies the type of the hart.
@@ -67,8 +69,6 @@ properties:
       lowercase to simplify parsing.
 
   timebase-frequency:
-    type: integer
-    minimum: 1
     description:
       Specifies the clock frequency of the system timer in Hz.
       This value is common to all harts on a single system image.
@@ -102,9 +102,9 @@ examples:
     cpus {
         #address-cells = <1>;
         #size-cells = <0>;
-        timebase-frequency = <1000000>;
         cpu@0 {
                 clock-frequency = <0>;
+                timebase-frequency = <1000000>;
                 compatible = "sifive,rocket0", "riscv";
                 device_type = "cpu";
                 i-cache-block-size = <64>;
@@ -120,6 +120,7 @@ examples:
         };
         cpu@1 {
                 clock-frequency = <0>;
+                timebase-frequency = <1000000>;
                 compatible = "sifive,rocket0", "riscv";
                 d-cache-block-size = <64>;
                 d-cache-sets = <64>;
@@ -153,6 +154,7 @@ examples:
                 device_type = "cpu";
                 reg = <0>;
                 compatible = "riscv";
+                timebase-frequency = <1000000>;
                 riscv,isa = "rv64imafdc";
                 mmu-type = "riscv,sv48";
                 interrupt-controller {
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-09-25 13:12 [PATCH v2] dt-bindings: riscv: Fix CPU schema errors Rob Herring
@ 2019-09-25 21:24 ` Palmer Dabbelt
  2019-09-25 23:29   ` Rob Herring
  0 siblings, 1 reply; 8+ messages in thread
From: Palmer Dabbelt @ 2019-09-25 21:24 UTC (permalink / raw)
  To: robh; +Cc: devicetree, linux-riscv, aou, linux-kernel, Paul Walmsley

On Wed, 25 Sep 2019 06:12:52 PDT (-0700), robh@kernel.org wrote:
> Fix the errors in the RiscV CPU DT schema:
>
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
>
> Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: linux-riscv@lists.infradead.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> v2:
>  - Add timebase-frequency to simulator example.
>
>  .../devicetree/bindings/riscv/cpus.yaml       | 26 ++++++++++---------
>  1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index b261a3015f84..eb0ef19829b6 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -24,15 +24,17 @@ description: |
>
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - sifive,rocket0
> -          - sifive,e5
> -          - sifive,e51
> -          - sifive,u54-mc
> -          - sifive,u54
> -          - sifive,u5
> -      - const: riscv
> +    oneOf:
> +      - items:
> +          - enum:
> +              - sifive,rocket0
> +              - sifive,e5
> +              - sifive,e51
> +              - sifive,u54-mc
> +              - sifive,u54
> +              - sifive,u5
> +          - const: riscv
> +      - const: riscv    # Simulator only
>      description:
>        Identifies that the hart uses the RISC-V instruction set
>        and identifies the type of the hart.
> @@ -67,8 +69,6 @@ properties:
>        lowercase to simplify parsing.
>
>    timebase-frequency:
> -    type: integer
> -    minimum: 1
>      description:
>        Specifies the clock frequency of the system timer in Hz.
>        This value is common to all harts on a single system image.
> @@ -102,9 +102,9 @@ examples:
>      cpus {
>          #address-cells = <1>;
>          #size-cells = <0>;
> -        timebase-frequency = <1000000>;
>          cpu@0 {
>                  clock-frequency = <0>;
> +                timebase-frequency = <1000000>;
>                  compatible = "sifive,rocket0", "riscv";
>                  device_type = "cpu";
>                  i-cache-block-size = <64>;
> @@ -120,6 +120,7 @@ examples:
>          };
>          cpu@1 {
>                  clock-frequency = <0>;
> +                timebase-frequency = <1000000>;
>                  compatible = "sifive,rocket0", "riscv";
>                  d-cache-block-size = <64>;
>                  d-cache-sets = <64>;
> @@ -153,6 +154,7 @@ examples:
>                  device_type = "cpu";
>                  reg = <0>;
>                  compatible = "riscv";
> +                timebase-frequency = <1000000>;
>                  riscv,isa = "rv64imafdc";
>                  mmu-type = "riscv,sv48";
>                  interrupt-controller {

Looking at this spec

    https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf

section 3.7 says

    Properties that have identical values across cpu nodes may be placed in the 
    /cpus node instead. A client program must
    first examine a specific cpu node, but if an expected property is not found 
    then it should look at the parent /cpus node.
    This results in a less verbose representation of properties which are 
    identical across all CPUs.

I can never figure out if I'm looking at the right DT specifications so it's 
possible that is defunct, I just bring this up because we've got an outstanding 
bug in our port where we're not respecting what section 3.7 says and are only 
looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency, 
and I'm wondering if the fix should allow for looking at 
/cpus/timebase-frequency or just not bother.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-09-25 21:24 ` Palmer Dabbelt
@ 2019-09-25 23:29   ` Rob Herring
  2019-10-08 20:36     ` Paul Walmsley
  0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2019-09-25 23:29 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: devicetree, linux-riscv, Albert Ou, linux-kernel, Paul Walmsley

On Wed, Sep 25, 2019 at 4:24 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Wed, 25 Sep 2019 06:12:52 PDT (-0700), robh@kernel.org wrote:
> > Fix the errors in the RiscV CPU DT schema:
> >
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> >
> > Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> > Cc: Paul Walmsley <paul.walmsley@sifive.com>
> > Cc: Palmer Dabbelt <palmer@sifive.com>
> > Cc: Albert Ou <aou@eecs.berkeley.edu>
> > Cc: linux-riscv@lists.infradead.org
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> > v2:
> >  - Add timebase-frequency to simulator example.
> >
> >  .../devicetree/bindings/riscv/cpus.yaml       | 26 ++++++++++---------
> >  1 file changed, 14 insertions(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index b261a3015f84..eb0ef19829b6 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -24,15 +24,17 @@ description: |
> >
> >  properties:
> >    compatible:
> > -    items:
> > -      - enum:
> > -          - sifive,rocket0
> > -          - sifive,e5
> > -          - sifive,e51
> > -          - sifive,u54-mc
> > -          - sifive,u54
> > -          - sifive,u5
> > -      - const: riscv
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - sifive,rocket0
> > +              - sifive,e5
> > +              - sifive,e51
> > +              - sifive,u54-mc
> > +              - sifive,u54
> > +              - sifive,u5
> > +          - const: riscv
> > +      - const: riscv    # Simulator only
> >      description:
> >        Identifies that the hart uses the RISC-V instruction set
> >        and identifies the type of the hart.
> > @@ -67,8 +69,6 @@ properties:
> >        lowercase to simplify parsing.
> >
> >    timebase-frequency:
> > -    type: integer
> > -    minimum: 1
> >      description:
> >        Specifies the clock frequency of the system timer in Hz.
> >        This value is common to all harts on a single system image.
> > @@ -102,9 +102,9 @@ examples:
> >      cpus {
> >          #address-cells = <1>;
> >          #size-cells = <0>;
> > -        timebase-frequency = <1000000>;
> >          cpu@0 {
> >                  clock-frequency = <0>;
> > +                timebase-frequency = <1000000>;
> >                  compatible = "sifive,rocket0", "riscv";
> >                  device_type = "cpu";
> >                  i-cache-block-size = <64>;
> > @@ -120,6 +120,7 @@ examples:
> >          };
> >          cpu@1 {
> >                  clock-frequency = <0>;
> > +                timebase-frequency = <1000000>;
> >                  compatible = "sifive,rocket0", "riscv";
> >                  d-cache-block-size = <64>;
> >                  d-cache-sets = <64>;
> > @@ -153,6 +154,7 @@ examples:
> >                  device_type = "cpu";
> >                  reg = <0>;
> >                  compatible = "riscv";
> > +                timebase-frequency = <1000000>;
> >                  riscv,isa = "rv64imafdc";
> >                  mmu-type = "riscv,sv48";
> >                  interrupt-controller {
>
> Looking at this spec
>
>     https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
>
> section 3.7 says
>
>     Properties that have identical values across cpu nodes may be placed in the
>     /cpus node instead. A client program must
>     first examine a specific cpu node, but if an expected property is not found
>     then it should look at the parent /cpus node.
>     This results in a less verbose representation of properties which are
>     identical across all CPUs.

The cpu sections of the spec are certainly not perfect. They are
largely from PPC with only the most obviously things wrong fixed...

> I can never figure out if I'm looking at the right DT specifications so it's
> possible that is defunct,

Why? What's not clear which one to look at? If you start at
devicetree.org the above is where you end up.

> I just bring this up because we've got an outstanding
> bug in our port where we're not respecting what section 3.7 says and are only
> looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency,
> and I'm wondering if the fix should allow for looking at
> /cpus/timebase-frequency or just not bother.

It's perfectly fine for some deviation for each arch or being more
restrictive. For Arm, we've generally gone the direction of everything
goes into the cpu nodes. So tell me what you want, I just need the
warnings gone.

Rob

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-09-25 23:29   ` Rob Herring
@ 2019-10-08 20:36     ` Paul Walmsley
  0 siblings, 0 replies; 8+ messages in thread
From: Paul Walmsley @ 2019-10-08 20:36 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, linux-riscv, Palmer Dabbelt, linux-kernel, Albert Ou

On Wed, 25 Sep 2019, Rob Herring wrote:

> On Wed, Sep 25, 2019 at 4:24 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> >
> > On Wed, 25 Sep 2019 06:12:52 PDT (-0700), robh@kernel.org wrote:
> > > Fix the errors in the RiscV CPU DT schema:
> > >
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > >
> > > Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> > > Cc: Paul Walmsley <paul.walmsley@sifive.com>
> > > Cc: Palmer Dabbelt <palmer@sifive.com>
> > > Cc: Albert Ou <aou@eecs.berkeley.edu>
> > > Cc: linux-riscv@lists.infradead.org
> > > Signed-off-by: Rob Herring <robh@kernel.org>
> > > ---
> > > v2:
> > >  - Add timebase-frequency to simulator example.
> > >
> > >  .../devicetree/bindings/riscv/cpus.yaml       | 26 ++++++++++---------
> > >  1 file changed, 14 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index b261a3015f84..eb0ef19829b6 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -24,15 +24,17 @@ description: |
> > >
> > >  properties:
> > >    compatible:
> > > -    items:
> > > -      - enum:
> > > -          - sifive,rocket0
> > > -          - sifive,e5
> > > -          - sifive,e51
> > > -          - sifive,u54-mc
> > > -          - sifive,u54
> > > -          - sifive,u5
> > > -      - const: riscv
> > > +    oneOf:
> > > +      - items:
> > > +          - enum:
> > > +              - sifive,rocket0
> > > +              - sifive,e5
> > > +              - sifive,e51
> > > +              - sifive,u54-mc
> > > +              - sifive,u54
> > > +              - sifive,u5
> > > +          - const: riscv
> > > +      - const: riscv    # Simulator only
> > >      description:
> > >        Identifies that the hart uses the RISC-V instruction set
> > >        and identifies the type of the hart.

The above part of this patch looks fine to me, and please consider that 
portion of this patch acked.

> > > @@ -67,8 +69,6 @@ properties:
> > >        lowercase to simplify parsing.
> > >
> > >    timebase-frequency:
> > > -    type: integer
> > > -    minimum: 1
> > >      description:
> > >        Specifies the clock frequency of the system timer in Hz.
> > >        This value is common to all harts on a single system image.
> > > @@ -102,9 +102,9 @@ examples:
> > >      cpus {
> > >          #address-cells = <1>;
> > >          #size-cells = <0>;
> > > -        timebase-frequency = <1000000>;
> > >          cpu@0 {
> > >                  clock-frequency = <0>;
> > > +                timebase-frequency = <1000000>;
> > >                  compatible = "sifive,rocket0", "riscv";
> > >                  device_type = "cpu";
> > >                  i-cache-block-size = <64>;
> > > @@ -120,6 +120,7 @@ examples:
> > >          };
> > >          cpu@1 {
> > >                  clock-frequency = <0>;
> > > +                timebase-frequency = <1000000>;
> > >                  compatible = "sifive,rocket0", "riscv";
> > >                  d-cache-block-size = <64>;
> > >                  d-cache-sets = <64>;
> > > @@ -153,6 +154,7 @@ examples:
> > >                  device_type = "cpu";
> > >                  reg = <0>;
> > >                  compatible = "riscv";
> > > +                timebase-frequency = <1000000>;
> > >                  riscv,isa = "rv64imafdc";
> > >                  mmu-type = "riscv,sv48";
> > >                  interrupt-controller {
> >
> > Looking at this spec
> >
> >     https://github.com/devicetree-org/devicetree-specification/releases/download/v0.2/devicetree-specification-v0.2.pdf
> >
> > section 3.7 says
> >
> >     Properties that have identical values across cpu nodes may be placed in the
> >     /cpus node instead. A client program must
> >     first examine a specific cpu node, but if an expected property is not found
> >     then it should look at the parent /cpus node.
> >     This results in a less verbose representation of properties which are
> >     identical across all CPUs.
> 
> The cpu sections of the spec are certainly not perfect. They are
> largely from PPC with only the most obviously things wrong fixed...

[ ... ]

> > I just bring this up because we've got an outstanding
> > bug in our port where we're not respecting what section 3.7 says and are only
> > looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency,
> > and I'm wondering if the fix should allow for looking at
> > /cpus/timebase-frequency or just not bother.
> 
> It's perfectly fine for some deviation for each arch or being more
> restrictive. For Arm, we've generally gone the direction of everything
> goes into the cpu nodes. So tell me what you want, I just need the
> warnings gone.

We probably should keep the timebase-frequency at the /cpus level, since 
that's how the current public silicon behaves, and that's how our kernel 
code currently works.  Do you want to patch the schemas for that, or would 
you like us to?


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-10-10 12:44   ` Rob Herring
@ 2019-10-10 18:34     ` Paul Walmsley
  0 siblings, 0 replies; 8+ messages in thread
From: Paul Walmsley @ 2019-10-10 18:34 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, linux-riscv, Palmer Dabbelt, linux-kernel, Albert Ou

On Thu, 10 Oct 2019, Rob Herring wrote:

> On Wed, Oct 9, 2019 at 7:08 PM Paul Walmsley <paul.walmsley@sifive.com> wrote:
> >
> > On Wed, 9 Oct 2019, Rob Herring wrote:
> >
> > > Fix the errors in the RiscV CPU DT schema:
> > >
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> > > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > >
> > > The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
> > > and RiscV is doing nothing special with it, so just drop the definition
> > > here and don't make it required.
> >
> > The RISC-V kernel code does in fact parse it and use it, and we currently
> > rely on it being under /cpus:
> >
> >   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/kernel/time.c#n19
> >
> > The RISC-V user ISA specification also constrains the timebase-frequency
> > to be the same across all CPUs, in section 10.1:
> >
> >   https://github.com/riscv/riscv-isa-manual/releases/download/draft-20190608-f467e5d/riscv-spec.pdf
> >
> > So the right thing is to require 'timebase-frequency' at /cpus, and forbid
> > it in the individual CPU nodes.
> 
> Yes, but this schema only deals with 'cpu' nodes and we can't check
> /cpus here. We'd need to write another schema matching on a child cpu
> node having a RiscV compatible.
> 
> I can change this to 'timebase-frequency: false' to ban it here.

Sounds good to me.  (Might catch the occasional mistake.)  With that 
change, the resulting patch would be

Acked-by: Paul Walmsley <paul.walmsley@sifive.com> # for arch/riscv

and thanks indeed for cleaning this up.

> That doesn't add too much as any undefined name is still allowed such as 
> 'timbase-frequency'. There's a way to address this in json-schema draft8 
> with 'unevaluatedProperties', but that's not ready yet.

OK


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-10-10  0:08 ` Paul Walmsley
@ 2019-10-10 12:44   ` Rob Herring
  2019-10-10 18:34     ` Paul Walmsley
  0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2019-10-10 12:44 UTC (permalink / raw)
  To: Paul Walmsley
  Cc: devicetree, linux-riscv, Palmer Dabbelt, linux-kernel, Albert Ou

On Wed, Oct 9, 2019 at 7:08 PM Paul Walmsley <paul.walmsley@sifive.com> wrote:
>
> On Wed, 9 Oct 2019, Rob Herring wrote:
>
> > Fix the errors in the RiscV CPU DT schema:
> >
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> > Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> >
> > The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
> > and RiscV is doing nothing special with it, so just drop the definition
> > here and don't make it required.
>
> The RISC-V kernel code does in fact parse it and use it, and we currently
> rely on it being under /cpus:
>
>   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/kernel/time.c#n19
>
> The RISC-V user ISA specification also constrains the timebase-frequency
> to be the same across all CPUs, in section 10.1:
>
>   https://github.com/riscv/riscv-isa-manual/releases/download/draft-20190608-f467e5d/riscv-spec.pdf
>
> So the right thing is to require 'timebase-frequency' at /cpus, and forbid
> it in the individual CPU nodes.

Yes, but this schema only deals with 'cpu' nodes and we can't check
/cpus here. We'd need to write another schema matching on a child cpu
node having a RiscV compatible.

I can change this to 'timebase-frequency: false' to ban it here. That
doesn't add too much as any undefined name is still allowed such as
'timbase-frequency'. There's a way to address this in json-schema
draft8 with 'unevaluatedProperties', but that's not ready yet.

Rob

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
  2019-10-09 23:46 Rob Herring
@ 2019-10-10  0:08 ` Paul Walmsley
  2019-10-10 12:44   ` Rob Herring
  0 siblings, 1 reply; 8+ messages in thread
From: Paul Walmsley @ 2019-10-10  0:08 UTC (permalink / raw)
  To: Rob Herring
  Cc: devicetree, linux-riscv, Palmer Dabbelt, linux-kernel, Albert Ou

On Wed, 9 Oct 2019, Rob Herring wrote:

> Fix the errors in the RiscV CPU DT schema:
> 
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
> Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
> 
> The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
> and RiscV is doing nothing special with it, so just drop the definition
> here and don't make it required.

The RISC-V kernel code does in fact parse it and use it, and we currently 
rely on it being under /cpus:

  https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/riscv/kernel/time.c#n19

The RISC-V user ISA specification also constrains the timebase-frequency 
to be the same across all CPUs, in section 10.1:

  https://github.com/riscv/riscv-isa-manual/releases/download/draft-20190608-f467e5d/riscv-spec.pdf

So the right thing is to require 'timebase-frequency' at /cpus, and forbid 
it in the individual CPU nodes. 

> 
> Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> Cc: Paul Walmsley <paul.walmsley@sifive.com>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Albert Ou <aou@eecs.berkeley.edu>
> Cc: linux-riscv@lists.infradead.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/riscv/cpus.yaml       | 28 ++++++++-----------
>  1 file changed, 11 insertions(+), 17 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index b261a3015f84..925b531767bf 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -24,15 +24,17 @@ description: |
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - sifive,rocket0
> -          - sifive,e5
> -          - sifive,e51
> -          - sifive,u54-mc
> -          - sifive,u54
> -          - sifive,u5
> -      - const: riscv
> +    oneOf:
> +      - items:
> +          - enum:
> +              - sifive,rocket0
> +              - sifive,e5
> +              - sifive,e51
> +              - sifive,u54-mc
> +              - sifive,u54
> +              - sifive,u5
> +          - const: riscv
> +      - const: riscv    # Simulator only
>      description:
>        Identifies that the hart uses the RISC-V instruction set
>        and identifies the type of the hart.
> @@ -66,13 +68,6 @@ properties:
>        insensitive, letters in the riscv,isa string must be all
>        lowercase to simplify parsing.
>  
> -  timebase-frequency:
> -    type: integer
> -    minimum: 1
> -    description:
> -      Specifies the clock frequency of the system timer in Hz.
> -      This value is common to all harts on a single system image.
> -
>    interrupt-controller:
>      type: object
>      description: Describes the CPU's local interrupt controller
> @@ -93,7 +88,6 @@ properties:
>  
>  required:
>    - riscv,isa
> -  - timebase-frequency
>    - interrupt-controller
>  
>  examples:
> -- 
> 2.20.1
> 
> 


- Paul

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2] dt-bindings: riscv: Fix CPU schema errors
@ 2019-10-09 23:46 Rob Herring
  2019-10-10  0:08 ` Paul Walmsley
  0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2019-10-09 23:46 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt
  Cc: devicetree, linux-riscv, Albert Ou, linux-kernel

Fix the errors in the RiscV CPU DT schema:

Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property

The DT spec allows for 'timebase-frequency' to be in 'cpu' or 'cpus' node
and RiscV is doing nothing special with it, so just drop the definition
here and don't make it required.

Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/riscv/cpus.yaml       | 28 ++++++++-----------
 1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index b261a3015f84..925b531767bf 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -24,15 +24,17 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,rocket0
-          - sifive,e5
-          - sifive,e51
-          - sifive,u54-mc
-          - sifive,u54
-          - sifive,u5
-      - const: riscv
+    oneOf:
+      - items:
+          - enum:
+              - sifive,rocket0
+              - sifive,e5
+              - sifive,e51
+              - sifive,u54-mc
+              - sifive,u54
+              - sifive,u5
+          - const: riscv
+      - const: riscv    # Simulator only
     description:
       Identifies that the hart uses the RISC-V instruction set
       and identifies the type of the hart.
@@ -66,13 +68,6 @@ properties:
       insensitive, letters in the riscv,isa string must be all
       lowercase to simplify parsing.
 
-  timebase-frequency:
-    type: integer
-    minimum: 1
-    description:
-      Specifies the clock frequency of the system timer in Hz.
-      This value is common to all harts on a single system image.
-
   interrupt-controller:
     type: object
     description: Describes the CPU's local interrupt controller
@@ -93,7 +88,6 @@ properties:
 
 required:
   - riscv,isa
-  - timebase-frequency
   - interrupt-controller
 
 examples:
-- 
2.20.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, back to index

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-25 13:12 [PATCH v2] dt-bindings: riscv: Fix CPU schema errors Rob Herring
2019-09-25 21:24 ` Palmer Dabbelt
2019-09-25 23:29   ` Rob Herring
2019-10-08 20:36     ` Paul Walmsley
2019-10-09 23:46 Rob Herring
2019-10-10  0:08 ` Paul Walmsley
2019-10-10 12:44   ` Rob Herring
2019-10-10 18:34     ` Paul Walmsley

Linux-RISC-V Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-riscv/0 linux-riscv/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-riscv linux-riscv/ https://lore.kernel.org/linux-riscv \
		linux-riscv@lists.infradead.org
	public-inbox-index linux-riscv

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-riscv


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git