[PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

[PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

[Samuel Holland]

This patch series adds PLIC support for Renesas RZ/Five SoC.

Since the T-HEAD C900 PLIC has the same behavior, it also applies the
fix for that variant.

This series is an update of v2 of the RZ/Five series[0], and replaces
the separate T-HEAD series[1].

[0]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
[1]: https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/

Changes in v3:
 - Add a more detailed explanation for why #interrupt-cells differs
 - Add andestech,nceplic100 as a fallback compatible
 - Separate the conditional part of the binding into two blocks (one for
   the PLIC implementation and the other for the SoC integration)
 - Use a quirk bit for selecting the flow instead of a variant ID
 - Use the andestech,nceplic100 compatible to select the new behavior
 - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
   always gets called
 - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL
 - Use the same name for plic_edge_chip as plic_chip

Changes in v2:
 - Fixed review comments pointed by Marc and Krzysztof.

Changes in v1:
 - Fixed review comments pointed by Rob and Geert.
 - Changed implementation for EDGE interrupt handling on Renesas RZ/Five
   SoC.

Lad Prabhakar (2):
  dt-bindings: interrupt-controller: sifive,plic: Document Renesas
    RZ/Five SoC
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

Samuel Holland (2):
  dt-bindings: interrupt-controller: Require trigger type for T-HEAD
    PLIC
  irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling

 .../sifive,plic-1.0.0.yaml                    | 65 +++++++++++++--
 drivers/irqchip/irq-sifive-plic.c             | 80 +++++++++++++++++--
 2 files changed, 135 insertions(+), 10 deletions(-)

-- 
2.35.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v3 1/4] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Samuel Holland]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Renesas RZ/Five (R9A07G043) SoC is equipped with NCEPLIC100 RISC-V
platform level interrupt controller from Andes Technology. NCEPLIC100
ignores subsequent EDGE interrupts until the previous EDGE interrupt is
completed, due to this issue we have to follow different interrupt flow
for EDGE and LEVEL interrupts.

This patch documents Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v3:
 - Add a more detailed explanation for why #interrupt-cells differs
 - Add andestech,nceplic100 as a fallback compatible
 - Separate the conditional part of the binding into two blocks (one for
   the PLIC implementation and the other for the SoC integration)

 .../sifive,plic-1.0.0.yaml                    | 64 +++++++++++++++++--
 1 file changed, 59 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..cd2b8bcaec3b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -26,9 +26,14 @@ description:
   with priority below this threshold will not cause the PLIC to raise its
   interrupt line leading to the context.
 
-  While the PLIC supports both edge-triggered and level-triggered interrupts,
-  interrupt handlers are oblivious to this distinction and therefore it is not
-  specified in the PLIC device-tree binding.
+  The PLIC supports both edge-triggered and level-triggered interrupts. For
+  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
+  seen while an interrupt handler is active; the PLIC may either queue them or
+  ignore them. In the first case, handlers are oblivious to the trigger type, so
+  it is not included in the interrupt specifier. In the second case, software
+  needs to know the trigger type, so it can reorder the interrupt flow to avoid
+  missing interrupts. This special handling is needed by at least the Renesas
+  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100).
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -47,6 +52,10 @@ maintainers:
 properties:
   compatible:
     oneOf:
+      - items:
+          - enum:
+              - renesas,r9a07g043-plic
+          - const: andestech,nceplic100
       - items:
           - enum:
               - sifive,fu540-c000-plic
@@ -64,8 +73,7 @@ properties:
   '#address-cells':
     const: 0
 
-  '#interrupt-cells':
-    const: 1
+  '#interrupt-cells': true
 
   interrupt-controller: true
 
@@ -82,6 +90,12 @@ properties:
     description:
       Specifies how many external interrupts are supported by this controller.
 
+  clocks: true
+
+  power-domains: true
+
+  resets: true
+
 required:
   - compatible
   - '#address-cells'
@@ -91,6 +105,46 @@ required:
   - interrupts-extended
   - riscv,ndev
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - andestech,nceplic100
+
+    then:
+      properties:
+        '#interrupt-cells':
+          const: 2
+
+    else:
+      properties:
+        '#interrupt-cells':
+          const: 1
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043-plic
+
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        power-domains:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+      required:
+        - clocks
+        - power-domains
+        - resets
+
 additionalProperties: false
 
 examples:
-- 
2.35.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v3 2/4] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Samuel Holland]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
edge until the previous completion message has been received and
NCEPLIC100 doesn't support pending interrupt counter, hence losing the
interrupts if not acknowledged in time.

So the workaround for edge-triggered interrupts to be handled correctly
and without losing is that it needs to be acknowledged first and then
handler must be run so that we don't miss on the next edge-triggered
interrupt.

This patch adds a new compatible string for NCEPLIC100 (from Andes
Technology) interrupt controller found on Renesas RZ/Five SoC and adds
quirk bits to priv structure and implements PLIC_QUIRK_EDGE_INTERRUPT
quirk to change the interrupt flow.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v3:
 - Use a quirk bit for selecting the flow instead of a variant ID
 - Use the andestech,nceplic100 compatible to select the new behavior
 - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
   always gets called
 - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL
 - Use the same name for plic_edge_chip as plic_chip

Changes in v2:
 - Fixed review comments pointed by Marc and Krzysztof.

Changes in v1:
 - Fixed review comments pointed by Rob and Geert.
 - Changed implementation for EDGE interrupt handling on Renesas RZ/Five
   SoC.

 drivers/irqchip/irq-sifive-plic.c | 78 +++++++++++++++++++++++++++++--
 1 file changed, 74 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..90e44367bee9 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,10 +60,13 @@
 #define	PLIC_DISABLE_THRESHOLD		0x7
 #define	PLIC_ENABLE_THRESHOLD		0
 
+#define PLIC_QUIRK_EDGE_INTERRUPT	0
+
 struct plic_priv {
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
+	unsigned long plic_quirks;
 };
 
 struct plic_handler {
@@ -81,6 +84,8 @@ static int plic_parent_irq __ro_after_init;
 static bool plic_cpuhp_setup_done __ro_after_init;
 static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type);
+
 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
 {
 	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
@@ -176,6 +181,17 @@ static void plic_irq_eoi(struct irq_data *d)
 	}
 }
 
+static struct irq_chip plic_edge_chip = {
+	.name		= "SiFive PLIC",
+	.irq_ack	= plic_irq_eoi,
+	.irq_mask	= plic_irq_mask,
+	.irq_unmask	= plic_irq_unmask,
+#ifdef CONFIG_SMP
+	.irq_set_affinity = plic_set_affinity,
+#endif
+	.irq_set_type	= plic_irq_set_type,
+};
+
 static struct irq_chip plic_chip = {
 	.name		= "SiFive PLIC",
 	.irq_mask	= plic_irq_mask,
@@ -184,8 +200,32 @@ static struct irq_chip plic_chip = {
 #ifdef CONFIG_SMP
 	.irq_set_affinity = plic_set_affinity,
 #endif
+	.irq_set_type	= plic_irq_set_type,
 };
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
+
+	if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
+		return IRQ_SET_MASK_OK_NOCOPY;
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_RISING:
+		irq_set_chip_handler_name_locked(d, &plic_edge_chip,
+						 handle_edge_irq, NULL);
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		irq_set_chip_handler_name_locked(d, &plic_chip,
+						 handle_fasteoi_irq, NULL);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return IRQ_SET_MASK_OK;
+}
+
 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 			      irq_hw_number_t hwirq)
 {
@@ -198,6 +238,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 	return 0;
 }
 
+static int plic_irq_domain_translate(struct irq_domain *d,
+				     struct irq_fwspec *fwspec,
+				     unsigned long *hwirq,
+				     unsigned int *type)
+{
+	struct plic_priv *priv = d->host_data;
+
+	if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks))
+		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
+
+	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
+}
+
 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 				 unsigned int nr_irqs, void *arg)
 {
@@ -206,7 +259,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	unsigned int type;
 	struct irq_fwspec *fwspec = arg;
 
-	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
 	if (ret)
 		return ret;
 
@@ -220,7 +273,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 }
 
 static const struct irq_domain_ops plic_irqdomain_ops = {
-	.translate	= irq_domain_translate_onecell,
+	.translate	= plic_irq_domain_translate,
 	.alloc		= plic_irq_domain_alloc,
 	.free		= irq_domain_free_irqs_top,
 };
@@ -281,8 +334,9 @@ static int plic_starting_cpu(unsigned int cpu)
 	return 0;
 }
 
-static int __init plic_init(struct device_node *node,
-		struct device_node *parent)
+static int __init __plic_init(struct device_node *node,
+			      struct device_node *parent,
+			      unsigned long plic_quirks)
 {
 	int error = 0, nr_contexts, nr_handlers = 0, i;
 	u32 nr_irqs;
@@ -293,6 +347,8 @@ static int __init plic_init(struct device_node *node,
 	if (!priv)
 		return -ENOMEM;
 
+	priv->plic_quirks = plic_quirks;
+
 	priv->regs = of_iomap(node, 0);
 	if (WARN_ON(!priv->regs)) {
 		error = -EIO;
@@ -410,6 +466,20 @@ static int __init plic_init(struct device_node *node,
 	return error;
 }
 
+static int __init plic_init(struct device_node *node,
+			    struct device_node *parent)
+{
+	return __plic_init(node, parent, 0);
+}
+
 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
+
+static int __init plic_edge_init(struct device_node *node,
+				 struct device_node *parent)
+{
+	return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT));
+}
+
+IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
-- 
2.35.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v3 3/4] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC

[Samuel Holland]

The RISC-V PLIC specification unfortunately allows PLIC implementations
to ignore edges seen while an edge-triggered interrupt is being handled:

  Depending on the design of the device and the interrupt handler,
  in between sending an interrupt request and receiving notice of its
  handler’s completion, the gateway might either ignore additional
  matching edges or increment a counter of pending interrupts.

Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus
it also needs to inform software about each interrupt's trigger type, so
the driver can use the right interrupt flow.

Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v3:
 - Rebased on top of the RZ/Five patches

 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml       | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index cd2b8bcaec3b..92e0f8c3eff2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -33,7 +33,7 @@ description:
   it is not included in the interrupt specifier. In the second case, software
   needs to know the trigger type, so it can reorder the interrupt flow to avoid
   missing interrupts. This special handling is needed by at least the Renesas
-  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100).
+  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -112,6 +112,7 @@ allOf:
           contains:
             enum:
               - andestech,nceplic100
+              - thead,c900-plic
 
     then:
       properties:
-- 
2.35.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v3 4/4] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling

[Samuel Holland]

The T-HEAD PLIC ignores additional edges seen while an edge-triggered
interrupt is being handled. Because of this behavior, the driver needs
to complete edge-triggered interrupts in the .irq_ack callback before
handling them, instead of in the .irq_eoi callback afterward. Otherwise,
it could miss some interrupts.

Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
---

Changes in v3:
 - Rebased on top of the RZ/Five patches

 drivers/irqchip/irq-sifive-plic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 90e44367bee9..b3a36dca7f1b 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -474,7 +474,6 @@ static int __init plic_init(struct device_node *node,
 
 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
-IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
 
 static int __init plic_edge_init(struct device_node *node,
 				 struct device_node *parent)
@@ -483,3 +482,4 @@ static int __init plic_edge_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
+IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
-- 
2.35.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 4/4] irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling

[Guo Ren]

Reviewed-by: Guo Ren <guoren@kernel.org>

On Thu, Jun 30, 2022 at 6:02 PM Samuel Holland <samuel@sholland.org> wrote:
>
> The T-HEAD PLIC ignores additional edges seen while an edge-triggered
> interrupt is being handled. Because of this behavior, the driver needs
> to complete edge-triggered interrupts in the .irq_ack callback before
> handling them, instead of in the .irq_eoi callback afterward. Otherwise,
> it could miss some interrupts.
>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>
> Changes in v3:
>  - Rebased on top of the RZ/Five patches
>
>  drivers/irqchip/irq-sifive-plic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index 90e44367bee9..b3a36dca7f1b 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -474,7 +474,6 @@ static int __init plic_init(struct device_node *node,
>
>  IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
>  IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
> -IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
>
>  static int __init plic_edge_init(struct device_node *node,
>                                  struct device_node *parent)
> @@ -483,3 +482,4 @@ static int __init plic_edge_init(struct device_node *node,
>  }
>
>  IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init);
> +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

[Marc Zyngier]

On 2022-06-30 11:02, Samuel Holland wrote:
> This patch series adds PLIC support for Renesas RZ/Five SoC.
> 
> Since the T-HEAD C900 PLIC has the same behavior, it also applies the
> fix for that variant.
> 
> This series is an update of v2 of the RZ/Five series[0], and replaces
> the separate T-HEAD series[1].
> 
> [0]:
> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1]:
> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/
> 
> Changes in v3:
>  - Add a more detailed explanation for why #interrupt-cells differs
>  - Add andestech,nceplic100 as a fallback compatible
>  - Separate the conditional part of the binding into two blocks (one 
> for
>    the PLIC implementation and the other for the SoC integration)
>  - Use a quirk bit for selecting the flow instead of a variant ID
>  - Use the andestech,nceplic100 compatible to select the new behavior
>  - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
>    always gets called
>  - Do not set the handler name, as RISC-V selects 
> GENERIC_IRQ_SHOW_LEVEL
>  - Use the same name for plic_edge_chip as plic_chip
> 
> Changes in v2:
>  - Fixed review comments pointed by Marc and Krzysztof.
> 
> Changes in v1:
>  - Fixed review comments pointed by Rob and Geert.
>  - Changed implementation for EDGE interrupt handling on Renesas 
> RZ/Five
>    SoC.
> 
> Lad Prabhakar (2):
>   dt-bindings: interrupt-controller: sifive,plic: Document Renesas
>     RZ/Five SoC
>   irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
> 
> Samuel Holland (2):
>   dt-bindings: interrupt-controller: Require trigger type for T-HEAD
>     PLIC
>   irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
> 
>  .../sifive,plic-1.0.0.yaml                    | 65 +++++++++++++--
>  drivers/irqchip/irq-sifive-plic.c             | 80 +++++++++++++++++--
>  2 files changed, 135 insertions(+), 10 deletions(-)

I'm going to provisionally queue this into -next so that it
can get some testing. I'd still want the DT changes to be
Ack'ed before the next merge window though.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

[Palmer Dabbelt]

On Fri, 01 Jul 2022 07:28:48 PDT (-0700), Marc Zyngier wrote:
> On 2022-06-30 11:02, Samuel Holland wrote:
>> This patch series adds PLIC support for Renesas RZ/Five SoC.
>>
>> Since the T-HEAD C900 PLIC has the same behavior, it also applies the
>> fix for that variant.
>>
>> This series is an update of v2 of the RZ/Five series[0], and replaces
>> the separate T-HEAD series[1].
>>
>> [0]:
>> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>> [1]:
>> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/
>>
>> Changes in v3:
>>  - Add a more detailed explanation for why #interrupt-cells differs
>>  - Add andestech,nceplic100 as a fallback compatible
>>  - Separate the conditional part of the binding into two blocks (one
>> for
>>    the PLIC implementation and the other for the SoC integration)
>>  - Use a quirk bit for selecting the flow instead of a variant ID
>>  - Use the andestech,nceplic100 compatible to select the new behavior
>>  - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
>>    always gets called
>>  - Do not set the handler name, as RISC-V selects
>> GENERIC_IRQ_SHOW_LEVEL
>>  - Use the same name for plic_edge_chip as plic_chip
>>
>> Changes in v2:
>>  - Fixed review comments pointed by Marc and Krzysztof.
>>
>> Changes in v1:
>>  - Fixed review comments pointed by Rob and Geert.
>>  - Changed implementation for EDGE interrupt handling on Renesas
>> RZ/Five
>>    SoC.
>>
>> Lad Prabhakar (2):
>>   dt-bindings: interrupt-controller: sifive,plic: Document Renesas
>>     RZ/Five SoC
>>   irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
>>
>> Samuel Holland (2):
>>   dt-bindings: interrupt-controller: Require trigger type for T-HEAD
>>     PLIC
>>   irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
>>
>>  .../sifive,plic-1.0.0.yaml                    | 65 +++++++++++++--
>>  drivers/irqchip/irq-sifive-plic.c             | 80 +++++++++++++++++--
>>  2 files changed, 135 insertions(+), 10 deletions(-)
>
> I'm going to provisionally queue this into -next so that it
> can get some testing. I'd still want the DT changes to be
> Ack'ed before the next merge window though.

+David, as IIRC he still tests on SiFive hardware.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

Though I also wait for Rob on DT stuff (I saw the other thread), so not 
sure that helps any.

Thanks!

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

[Conor.Dooley]

On 13/07/2022 04:19, Palmer Dabbelt wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Fri, 01 Jul 2022 07:28:48 PDT (-0700), Marc Zyngier wrote:
>> On 2022-06-30 11:02, Samuel Holland wrote:
>>> This patch series adds PLIC support for Renesas RZ/Five SoC.
>>>
>>> Since the T-HEAD C900 PLIC has the same behavior, it also applies the
>>> fix for that variant.
>>>
>>> This series is an update of v2 of the RZ/Five series[0], and replaces
>>> the separate T-HEAD series[1].
>>>
>>> [0]:
>>> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
>>> [1]:
>>> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/
>>>
>>> Changes in v3:
>>>  - Add a more detailed explanation for why #interrupt-cells differs
>>>  - Add andestech,nceplic100 as a fallback compatible
>>>  - Separate the conditional part of the binding into two blocks (one
>>> for
>>>    the PLIC implementation and the other for the SoC integration)
>>>  - Use a quirk bit for selecting the flow instead of a variant ID
>>>  - Use the andestech,nceplic100 compatible to select the new behavior
>>>  - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
>>>    always gets called
>>>  - Do not set the handler name, as RISC-V selects
>>> GENERIC_IRQ_SHOW_LEVEL
>>>  - Use the same name for plic_edge_chip as plic_chip
>>>
>>> Changes in v2:
>>>  - Fixed review comments pointed by Marc and Krzysztof.
>>>
>>> Changes in v1:
>>>  - Fixed review comments pointed by Rob and Geert.
>>>  - Changed implementation for EDGE interrupt handling on Renesas
>>> RZ/Five
>>>    SoC.
>>>
>>> Lad Prabhakar (2):
>>>   dt-bindings: interrupt-controller: sifive,plic: Document Renesas
>>>     RZ/Five SoC
>>>   irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
>>>
>>> Samuel Holland (2):
>>>   dt-bindings: interrupt-controller: Require trigger type for T-HEAD
>>>     PLIC
>>>   irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
>>>
>>>  .../sifive,plic-1.0.0.yaml                    | 65 +++++++++++++--
>>>  drivers/irqchip/irq-sifive-plic.c             | 80 +++++++++++++++++--
>>>  2 files changed, 135 insertions(+), 10 deletions(-)
>>
>> I'm going to provisionally queue this into -next so that it
>> can get some testing. I'd still want the DT changes to be
>> Ack'ed before the next merge window though.
> 
> +David, as IIRC he still tests on SiFive hardware.

Not David, but FWIW:
I have not done any specific testing, but I've been running various
-next revisions since this was put in there (on PolarFire & u540)
and have not noticed anything obviously wrong.
Thanks,
Conor.

> 
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> 
> Though I also wait for Rob on DT stuff (I saw the other thread), so not
> sure that helps any.
> 
> Thanks!
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv