* [PATCH] riscv: enable software resend of irqs
@ 2022-07-29 11:11 Conor Dooley
2022-10-10 11:21 ` Björn Töpel
2022-10-13 19:45 ` Palmer Dabbelt
0 siblings, 2 replies; 6+ messages in thread
From: Conor Dooley @ 2022-07-29 11:11 UTC (permalink / raw)
To: aou, palmer, paul.walmsley, linux-riscv; +Cc: conor.dooley, samuel, dfustini
The PLIC specification does not describe the interrupt pendings bits as
read-write, only that they "can be read". To allow for retriggering of
interrupts (and the use of the irq debugfs interface) enable
HARDIRQS_SW_RESEND for RISC-V.
Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 55d2cc458ace..d8a132426c64 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -69,6 +69,7 @@ config RISCV
select GENERIC_SMP_IDLE_THREAD
select GENERIC_TIME_VSYSCALL if MMU && 64BIT
select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO
+ select HARDIRQS_SW_RESEND
select HAVE_ARCH_AUDITSYSCALL
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
select HAVE_ARCH_JUMP_LABEL_RELATIVE if !XIP_KERNEL
--
2.36.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: enable software resend of irqs
2022-07-29 11:11 [PATCH] riscv: enable software resend of irqs Conor Dooley
@ 2022-10-10 11:21 ` Björn Töpel
2022-10-13 1:13 ` Palmer Dabbelt
2022-10-13 19:45 ` Palmer Dabbelt
1 sibling, 1 reply; 6+ messages in thread
From: Björn Töpel @ 2022-10-10 11:21 UTC (permalink / raw)
To: Conor Dooley, aou, palmer, paul.walmsley, linux-riscv
Cc: conor.dooley, samuel, dfustini
Conor Dooley <conor.dooley@microchip.com> writes:
> The PLIC specification does not describe the interrupt pendings bits as
> read-write, only that they "can be read". To allow for retriggering of
> interrupts (and the use of the irq debugfs interface) enable
> HARDIRQS_SW_RESEND for RISC-V.
>
> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Waking up an old thread. FWIW,
Reviewed-by: Björn Töpel <bjorn@kernel.org>
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* Re: [PATCH] riscv: enable software resend of irqs
2022-10-10 11:21 ` Björn Töpel
@ 2022-10-13 1:13 ` Palmer Dabbelt
2022-10-13 10:20 ` Marc Zyngier
0 siblings, 1 reply; 6+ messages in thread
From: Palmer Dabbelt @ 2022-10-13 1:13 UTC (permalink / raw)
To: bjorn, Marc Zyngier, tglx
Cc: conor.dooley, aou, Paul Walmsley, linux-riscv, conor.dooley,
samuel, dfustini
On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote:
> Conor Dooley <conor.dooley@microchip.com> writes:
>
>> The PLIC specification does not describe the interrupt pendings bits as
>> read-write, only that they "can be read". To allow for retriggering of
>> interrupts (and the use of the irq debugfs interface) enable
>> HARDIRQS_SW_RESEND for RISC-V.
>>
>> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Waking up an old thread. FWIW,
>
> Reviewed-by: Björn Töpel <bjorn@kernel.org>
Thanks. This look reasonable to me, not sure if the irqchip folks have
an opinion though?
In theory the PLIC isn't the only interrupt controller (and that spec
predates most of the implementations), but the SiFive PLIC derived
interrupt controllers have become a defacto standard and IIRC they're
the only thing shipping right now so I think it's OK to just stick this
in arch code. We could mark it as "if SIFIVE_PLIC" or something, but I
don't know if that's worth doing.
Either way, this isn't really my thing. Happy to take it via the RISC-V
tree, but
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU
if you want it via the irqchip tree. I put it over at
palmer/riscv-irq_sw_resend in case you want to do a shared tree or
something, but that seems pretty overkill to me here. It's passing
all my tests, but that's just QEMU.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: enable software resend of irqs
2022-10-13 1:13 ` Palmer Dabbelt
@ 2022-10-13 10:20 ` Marc Zyngier
2022-10-13 19:48 ` Palmer Dabbelt
0 siblings, 1 reply; 6+ messages in thread
From: Marc Zyngier @ 2022-10-13 10:20 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: bjorn, tglx, conor.dooley, aou, Paul Walmsley, linux-riscv,
samuel, dfustini
On Thu, 13 Oct 2022 02:13:50 +0100,
Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote:
> > Conor Dooley <conor.dooley@microchip.com> writes:
> >
> >> The PLIC specification does not describe the interrupt pendings bits as
> >> read-write, only that they "can be read". To allow for retriggering of
> >> interrupts (and the use of the irq debugfs interface) enable
> >> HARDIRQS_SW_RESEND for RISC-V.
> >>
> >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >
> > Waking up an old thread. FWIW,
> >
> > Reviewed-by: Björn Töpel <bjorn@kernel.org>
>
> Thanks. This look reasonable to me, not sure if the irqchip folks
> have an opinion though?
>
> In theory the PLIC isn't the only interrupt controller (and that spec
> predates most of the implementations), but the SiFive PLIC derived
> interrupt controllers have become a defacto standard and IIRC they're
> the only thing shipping right now so I think it's OK to just stick
> this in arch code. We could mark it as "if SIFIVE_PLIC" or something,
> but I don't know if that's worth doing.
Setting it at the architecture level is at least consistent with what
other arches are doing. If we need to fix it one day, we'll do it
globally.
>
> Either way, this isn't really my thing. Happy to take it via the
> RISC-V tree, but
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU
Please take it directly, and feel free to add my
Acked-by: Marc Zyngier <maz@kernel.org>
to it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: enable software resend of irqs
2022-07-29 11:11 [PATCH] riscv: enable software resend of irqs Conor Dooley
2022-10-10 11:21 ` Björn Töpel
@ 2022-10-13 19:45 ` Palmer Dabbelt
1 sibling, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-10-13 19:45 UTC (permalink / raw)
To: Conor Dooley, aou, linux-riscv, Palmer Dabbelt, Paul Walmsley
Cc: samuel, dfustini
On Fri, 29 Jul 2022 12:11:17 +0100, Conor Dooley wrote:
> The PLIC specification does not describe the interrupt pendings bits as
> read-write, only that they "can be read". To allow for retriggering of
> interrupts (and the use of the irq debugfs interface) enable
> HARDIRQS_SW_RESEND for RISC-V.
>
>
Applied, thanks!
[1/1] riscv: enable software resend of irqs
https://git.kernel.org/palmer/c/c45fc916c2b2
Best regards,
--
Palmer Dabbelt <palmer@rivosinc.com>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: enable software resend of irqs
2022-10-13 10:20 ` Marc Zyngier
@ 2022-10-13 19:48 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-10-13 19:48 UTC (permalink / raw)
To: Marc Zyngier
Cc: bjorn, tglx, conor.dooley, aou, Paul Walmsley, linux-riscv,
samuel, dfustini
On Thu, 13 Oct 2022 03:20:00 PDT (-0700), Marc Zyngier wrote:
> On Thu, 13 Oct 2022 02:13:50 +0100,
> Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn@kernel.org wrote:
>> > Conor Dooley <conor.dooley@microchip.com> writes:
>> >
>> >> The PLIC specification does not describe the interrupt pendings bits as
>> >> read-write, only that they "can be read". To allow for retriggering of
>> >> interrupts (and the use of the irq debugfs interface) enable
>> >> HARDIRQS_SW_RESEND for RISC-V.
>> >>
>> >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
>> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> >
>> > Waking up an old thread. FWIW,
>> >
>> > Reviewed-by: Björn Töpel <bjorn@kernel.org>
>>
>> Thanks. This look reasonable to me, not sure if the irqchip folks
>> have an opinion though?
>>
>> In theory the PLIC isn't the only interrupt controller (and that spec
>> predates most of the implementations), but the SiFive PLIC derived
>> interrupt controllers have become a defacto standard and IIRC they're
>> the only thing shipping right now so I think it's OK to just stick
>> this in arch code. We could mark it as "if SIFIVE_PLIC" or something,
>> but I don't know if that's worth doing.
>
> Setting it at the architecture level is at least consistent with what
> other arches are doing. If we need to fix it one day, we'll do it
> globally.
Works for me.
>
>>
>> Either way, this isn't really my thing. Happy to take it via the
>> RISC-V tree, but
>> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>> Tested-by: Palmer Dabbelt <palmer@rivosinc.com> # on QEMU
>
> Please take it directly, and feel free to add my
>
> Acked-by: Marc Zyngier <maz@kernel.org>
>
> to it.
Thanks, it's on riscv/for-next.
>
> Thanks,
>
> M.
>
> --
> Without deviation from the norm, progress is not possible.
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2022-07-29 11:11 [PATCH] riscv: enable software resend of irqs Conor Dooley
2022-10-10 11:21 ` Björn Töpel
2022-10-13 1:13 ` Palmer Dabbelt
2022-10-13 10:20 ` Marc Zyngier
2022-10-13 19:48 ` Palmer Dabbelt
2022-10-13 19:45 ` Palmer Dabbelt
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