[PATCH v2 0/6] Use composable cache instead of L2 cache

[PATCH v2 0/6] Use composable cache instead of L2 cache

[Zong Li]

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name "composable cache" to prevent confusion.

This patchset contains the modification which is related to ccache, such
as DT binding and EDAC driver.

The DT binding is based on top of Conor's patch, it has got ready for
merging, and it looks that it would be taken into the next few 6.0-rc
version. If there is any change, the next version of this series will be
posted as well.
https://lore.kernel.org/linux-riscv/20220825180417.1259360-2-mail@conchuod.ie/

Ben Dooks (2):
  soc: sifive: ccache: reduce printing on init
  soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

Greentime Hu (1):
  soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

Zong Li (3):
  dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache
  soc: sifive: ccache: determine the cache level from dts
  EDAC/sifive: use sifive_ccache instead of sifive_l2

 ...five-l2-cache.yaml => sifive,ccache0.yaml} |  28 ++-
 drivers/edac/Kconfig                          |   2 +-
 drivers/edac/sifive_edac.c                    |  12 +-
 drivers/soc/sifive/Kconfig                    |   6 +-
 drivers/soc/sifive/Makefile                   |   2 +-
 .../{sifive_l2_cache.c => sifive_ccache.c}    | 183 +++++++++---------
 .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
 7 files changed, 136 insertions(+), 113 deletions(-)
 rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
 rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (34%)
 rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)

-- 
2.17.1


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[PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

[Zong Li]

Since composable cache may be L3 cache if private L2 cache exists, we
should use its original name Composable cache to prevent confusion.

Signed-off-by: Zong Li <zong.li@sifive.com>
Suggested-by: Conor Dooley <conor.dooley@microchip.com>
Suggested-by: Ben Dooks <ben.dooks@sifive.com>
---
 ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
 1 file changed, 23 insertions(+), 5 deletions(-)
 rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)

diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
similarity index 83%
rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index ca3b9be58058..bf3f07421f7e 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -2,18 +2,18 @@
 # Copyright (C) 2020 SiFive, Inc.
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
+$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: SiFive L2 Cache Controller
+title: SiFive Composable Cache Controller
 
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
 
 description:
-  The SiFive Level 2 Cache Controller is used to provide access to fast copies
-  of memory for masters in a Core Complex. The Level 2 Cache Controller also
+  The SiFive Composable Cache Controller is used to provide access to fast copies
+  of memory for masters in a Core Complex. The Composable Cache Controller also
   acts as directory-based coherency manager.
   All the properties in ePAPR/DeviceTree specification applies for this platform.
 
@@ -22,6 +22,7 @@ select:
     compatible:
       contains:
         enum:
+          - sifive,ccache0
           - sifive,fu540-c000-ccache
           - sifive,fu740-c000-ccache
 
@@ -33,6 +34,7 @@ properties:
     oneOf:
       - items:
           - enum:
+              - sifive,ccache0
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
           - const: cache
@@ -45,7 +47,7 @@ properties:
     const: 64
 
   cache-level:
-    const: 2
+    enum: [2, 3]
 
   cache-sets:
     enum: [1024, 2048]
@@ -115,6 +117,22 @@ allOf:
         cache-sets:
           const: 1024
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: sifive,ccache0
+
+    then:
+      properties:
+        cache-level:
+          enum: [2, 3]
+
+    else:
+      properties:
+        cache-level:
+          const: 2
+
 additionalProperties: false
 
 required:
-- 
2.17.1


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[PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Zong Li]

From: Greentime Hu <greentime.hu@sifive.com>

Since composable cache may be L3 cache if pL2 cache exists, we should use
its original name composable cache to prevent confusion.

Apart from renaming, we also add the compatible "sifive,ccache0" into ID
table.

Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/soc/sifive/Kconfig                    |   6 +-
 drivers/soc/sifive/Makefile                   |   2 +-
 .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
 .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
 4 files changed, 94 insertions(+), 93 deletions(-)
 rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
 rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)

diff --git a/drivers/soc/sifive/Kconfig b/drivers/soc/sifive/Kconfig
index 58cf8c40d08d..ed4c571f8771 100644
--- a/drivers/soc/sifive/Kconfig
+++ b/drivers/soc/sifive/Kconfig
@@ -2,9 +2,9 @@
 
 if SOC_SIFIVE
 
-config SIFIVE_L2
-	bool "Sifive L2 Cache controller"
+config SIFIVE_CCACHE
+	bool "Sifive Composable Cache controller"
 	help
-	  Support for the L2 cache controller on SiFive platforms.
+	  Support for the composable cache controller on SiFive platforms.
 
 endif
diff --git a/drivers/soc/sifive/Makefile b/drivers/soc/sifive/Makefile
index b5caff77938f..1f5dc339bf82 100644
--- a/drivers/soc/sifive/Makefile
+++ b/drivers/soc/sifive/Makefile
@@ -1,3 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 
-obj-$(CONFIG_SIFIVE_L2)	+= sifive_l2_cache.o
+obj-$(CONFIG_SIFIVE_CCACHE)	+= sifive_ccache.o
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
similarity index 35%
rename from drivers/soc/sifive/sifive_l2_cache.c
rename to drivers/soc/sifive/sifive_ccache.c
index 59640a1d0b28..1b16a196547f 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * SiFive L2 cache controller Driver
+ * SiFive composable cache controller Driver
  *
- * Copyright (C) 2018-2019 SiFive, Inc.
+ * Copyright (C) 2018-2022 SiFive, Inc.
  *
  */
 #include <linux/debugfs.h>
@@ -11,33 +11,33 @@
 #include <linux/of_address.h>
 #include <linux/device.h>
 #include <asm/cacheinfo.h>
-#include <soc/sifive/sifive_l2_cache.h>
+#include <soc/sifive/sifive_ccache.h>
 
-#define SIFIVE_L2_DIRECCFIX_LOW 0x100
-#define SIFIVE_L2_DIRECCFIX_HIGH 0x104
-#define SIFIVE_L2_DIRECCFIX_COUNT 0x108
+#define SIFIVE_CCACHE_DIRECCFIX_LOW 0x100
+#define SIFIVE_CCACHE_DIRECCFIX_HIGH 0x104
+#define SIFIVE_CCACHE_DIRECCFIX_COUNT 0x108
 
-#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
-#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
-#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
+#define SIFIVE_CCACHE_DIRECCFAIL_LOW 0x120
+#define SIFIVE_CCACHE_DIRECCFAIL_HIGH 0x124
+#define SIFIVE_CCACHE_DIRECCFAIL_COUNT 0x128
 
-#define SIFIVE_L2_DATECCFIX_LOW 0x140
-#define SIFIVE_L2_DATECCFIX_HIGH 0x144
-#define SIFIVE_L2_DATECCFIX_COUNT 0x148
+#define SIFIVE_CCACHE_DATECCFIX_LOW 0x140
+#define SIFIVE_CCACHE_DATECCFIX_HIGH 0x144
+#define SIFIVE_CCACHE_DATECCFIX_COUNT 0x148
 
-#define SIFIVE_L2_DATECCFAIL_LOW 0x160
-#define SIFIVE_L2_DATECCFAIL_HIGH 0x164
-#define SIFIVE_L2_DATECCFAIL_COUNT 0x168
+#define SIFIVE_CCACHE_DATECCFAIL_LOW 0x160
+#define SIFIVE_CCACHE_DATECCFAIL_HIGH 0x164
+#define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168
 
-#define SIFIVE_L2_CONFIG 0x00
-#define SIFIVE_L2_WAYENABLE 0x08
-#define SIFIVE_L2_ECCINJECTERR 0x40
+#define SIFIVE_CCACHE_CONFIG 0x00
+#define SIFIVE_CCACHE_WAYENABLE 0x08
+#define SIFIVE_CCACHE_ECCINJECTERR 0x40
 
-#define SIFIVE_L2_MAX_ECCINTR 4
+#define SIFIVE_CCACHE_MAX_ECCINTR 4
 
-static void __iomem *l2_base;
-static int g_irq[SIFIVE_L2_MAX_ECCINTR];
-static struct riscv_cacheinfo_ops l2_cache_ops;
+static void __iomem *ccache_base;
+static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
+static struct riscv_cacheinfo_ops ccache_cache_ops;
 
 enum {
 	DIR_CORR = 0,
@@ -49,7 +49,7 @@ enum {
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *sifive_test;
 
-static ssize_t l2_write(struct file *file, const char __user *data,
+static ssize_t ccache_write(struct file *file, const char __user *data,
 			size_t count, loff_t *ppos)
 {
 	unsigned int val;
@@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
 	if (kstrtouint_from_user(data, count, 0, &val))
 		return -EINVAL;
 	if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
-		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
+		writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
 	else
 		return -EINVAL;
 	return count;
 }
 
-static const struct file_operations l2_fops = {
+static const struct file_operations ccache_fops = {
 	.owner = THIS_MODULE,
 	.open = simple_open,
-	.write = l2_write
+	.write = ccache_write
 };
 
 static void setup_sifive_debug(void)
 {
-	sifive_test = debugfs_create_dir("sifive_l2_cache", NULL);
+	sifive_test = debugfs_create_dir("sifive_ccache_cache", NULL);
 
 	debugfs_create_file("sifive_debug_inject_error", 0200,
-			    sifive_test, NULL, &l2_fops);
+			    sifive_test, NULL, &ccache_fops);
 }
 #endif
 
-static void l2_config_read(void)
+static void ccache_config_read(void)
 {
 	u32 regval, val;
 
-	regval = readl(l2_base + SIFIVE_L2_CONFIG);
+	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
 	val = regval & 0xFF;
-	pr_info("L2CACHE: No. of Banks in the cache: %d\n", val);
+	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
 	val = (regval & 0xFF00) >> 8;
-	pr_info("L2CACHE: No. of ways per bank: %d\n", val);
+	pr_info("CCACHE: No. of ways per bank: %d\n", val);
 	val = (regval & 0xFF0000) >> 16;
-	pr_info("L2CACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
+	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
 	val = (regval & 0xFF000000) >> 24;
-	pr_info("L2CACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
+	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
 
-	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
-	pr_info("L2CACHE: Index of the largest way enabled: %d\n", regval);
+	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
 }
 
-static const struct of_device_id sifive_l2_ids[] = {
+static const struct of_device_id sifive_ccache_ids[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
+	{ .compatible = "sifive,ccache0" },
 	{ /* end of table */ },
 };
 
-static ATOMIC_NOTIFIER_HEAD(l2_err_chain);
+static ATOMIC_NOTIFIER_HEAD(ccache_err_chain);
 
-int register_sifive_l2_error_notifier(struct notifier_block *nb)
+int register_sifive_ccache_error_notifier(struct notifier_block *nb)
 {
-	return atomic_notifier_chain_register(&l2_err_chain, nb);
+	return atomic_notifier_chain_register(&ccache_err_chain, nb);
 }
-EXPORT_SYMBOL_GPL(register_sifive_l2_error_notifier);
+EXPORT_SYMBOL_GPL(register_sifive_ccache_error_notifier);
 
-int unregister_sifive_l2_error_notifier(struct notifier_block *nb)
+int unregister_sifive_ccache_error_notifier(struct notifier_block *nb)
 {
-	return atomic_notifier_chain_unregister(&l2_err_chain, nb);
+	return atomic_notifier_chain_unregister(&ccache_err_chain, nb);
 }
-EXPORT_SYMBOL_GPL(unregister_sifive_l2_error_notifier);
+EXPORT_SYMBOL_GPL(unregister_sifive_ccache_error_notifier);
 
-static int l2_largest_wayenabled(void)
+static int ccache_largest_wayenabled(void)
 {
-	return readl(l2_base + SIFIVE_L2_WAYENABLE) & 0xFF;
+	return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF;
 }
 
 static ssize_t number_of_ways_enabled_show(struct device *dev,
 					   struct device_attribute *attr,
 					   char *buf)
 {
-	return sprintf(buf, "%u\n", l2_largest_wayenabled());
+	return sprintf(buf, "%u\n", ccache_largest_wayenabled());
 }
 
 static DEVICE_ATTR_RO(number_of_ways_enabled);
@@ -139,99 +140,99 @@ static const struct attribute_group priv_attr_group = {
 	.attrs = priv_attrs,
 };
 
-static const struct attribute_group *l2_get_priv_group(struct cacheinfo *this_leaf)
+static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
 {
-	/* We want to use private group for L2 cache only */
+	/* We want to use private group for composable cache only */
 	if (this_leaf->level == 2)
 		return &priv_attr_group;
 	else
 		return NULL;
 }
 
-static irqreturn_t l2_int_handler(int irq, void *device)
+static irqreturn_t ccache_int_handler(int irq, void *device)
 {
 	unsigned int add_h, add_l;
 
 	if (irq == g_irq[DIR_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
-		pr_err("L2CACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
+		pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DirError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
+		readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
 					   "DirECCFix");
 	}
 	if (irq == g_irq[DIR_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW);
 		/* Reading this register clears the DirFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+		readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
 					   "DirECCFail");
-		panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
+		panic("CCACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
 	}
 	if (irq == g_irq[DATA_CORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
-		pr_err("L2CACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
+		pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataError interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
 					   "DatECCFix");
 	}
 	if (irq == g_irq[DATA_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
-		pr_err("L2CACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
+		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
+		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
+		pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
+		readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
+		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
 					   "DatECCFail");
 	}
 
 	return IRQ_HANDLED;
 }
 
-static int __init sifive_l2_init(void)
+static int __init sifive_ccache_init(void)
 {
 	struct device_node *np;
 	struct resource res;
 	int i, rc, intr_num;
 
-	np = of_find_matching_node(NULL, sifive_l2_ids);
+	np = of_find_matching_node(NULL, sifive_ccache_ids);
 	if (!np)
 		return -ENODEV;
 
 	if (of_address_to_resource(np, 0, &res))
 		return -ENODEV;
 
-	l2_base = ioremap(res.start, resource_size(&res));
-	if (!l2_base)
+	ccache_base = ioremap(res.start, resource_size(&res));
+	if (!ccache_base)
 		return -ENOMEM;
 
 	intr_num = of_property_count_u32_elems(np, "interrupts");
 	if (!intr_num) {
-		pr_err("L2CACHE: no interrupts property\n");
+		pr_err("CCACHE: no interrupts property\n");
 		return -ENODEV;
 	}
 
 	for (i = 0; i < intr_num; i++) {
 		g_irq[i] = irq_of_parse_and_map(np, i);
-		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
+		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
 		if (rc) {
-			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
+			pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
 			return rc;
 		}
 	}
 
-	l2_config_read();
+	ccache_config_read();
 
-	l2_cache_ops.get_priv_group = l2_get_priv_group;
-	riscv_set_cacheinfo_ops(&l2_cache_ops);
+	ccache_cache_ops.get_priv_group = ccache_get_priv_group;
+	riscv_set_cacheinfo_ops(&ccache_cache_ops);
 
 #ifdef CONFIG_DEBUG_FS
 	setup_sifive_debug();
 #endif
 	return 0;
 }
-device_initcall(sifive_l2_init);
+device_initcall(sifive_ccache_init);
diff --git a/include/soc/sifive/sifive_l2_cache.h b/include/soc/sifive/sifive_ccache.h
similarity index 12%
rename from include/soc/sifive/sifive_l2_cache.h
rename to include/soc/sifive/sifive_ccache.h
index 92ade10ed67e..4d4ed49388a0 100644
--- a/include/soc/sifive/sifive_l2_cache.h
+++ b/include/soc/sifive/sifive_ccache.h
@@ -1,16 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * SiFive L2 Cache Controller header file
+ * SiFive Composable Cache Controller header file
  *
  */
 
-#ifndef __SOC_SIFIVE_L2_CACHE_H
-#define __SOC_SIFIVE_L2_CACHE_H
+#ifndef __SOC_SIFIVE_CCACHE_H
+#define __SOC_SIFIVE_CCACHE_H
 
-extern int register_sifive_l2_error_notifier(struct notifier_block *nb);
-extern int unregister_sifive_l2_error_notifier(struct notifier_block *nb);
+extern int register_sifive_ccache_error_notifier(struct notifier_block *nb);
+extern int unregister_sifive_ccache_error_notifier(struct notifier_block *nb);
 
-#define SIFIVE_L2_ERR_TYPE_CE 0
-#define SIFIVE_L2_ERR_TYPE_UE 1
+#define SIFIVE_CCACHE_ERR_TYPE_CE 0
+#define SIFIVE_CCACHE_ERR_TYPE_UE 1
 
-#endif /* __SOC_SIFIVE_L2_CACHE_H */
+#endif /* __SOC_SIFIVE_CCACHE_H */
-- 
2.17.1


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[PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts

[Zong Li]

Composable cache could be L2 or L3 cache, use 'cache-level' property of
device node to determine the level.

Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
---
 drivers/soc/sifive/sifive_ccache.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 1b16a196547f..0e0eb85c94d8 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -38,6 +38,7 @@
 static void __iomem *ccache_base;
 static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
 static struct riscv_cacheinfo_ops ccache_cache_ops;
+static int level;
 
 enum {
 	DIR_CORR = 0,
@@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
 static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
 {
 	/* We want to use private group for composable cache only */
-	if (this_leaf->level == 2)
+	if (this_leaf->level == level)
 		return &priv_attr_group;
 	else
 		return NULL;
@@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
 	if (!ccache_base)
 		return -ENOMEM;
 
+	if (of_property_read_u32(np, "cache-level", &level))
+		return -ENODEV;
+
 	intr_num = of_property_count_u32_elems(np, "interrupts");
 	if (!intr_num) {
 		pr_err("CCACHE: no interrupts property\n");
-- 
2.17.1


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[PATCH v2 4/6] soc: sifive: ccache: reduce printing on init

[Zong Li]

From: Ben Dooks <ben.dooks@sifive.com>

The driver prints out 6 lines on startup, which can easily be redcued
to two lines without losing any information.

Note, to make the types work better, uint64_t has been replaced with
ULL to make the unsigned long long match the format in the print
statement.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 0e0eb85c94d8..401c67a485e2 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
 
 static void ccache_config_read(void)
 {
-	u32 regval, val;
-
-	regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
-	val = regval & 0xFF;
-	pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
-	val = (regval & 0xFF00) >> 8;
-	pr_info("CCACHE: No. of ways per bank: %d\n", val);
-	val = (regval & 0xFF0000) >> 16;
-	pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
-	val = (regval & 0xFF000000) >> 24;
-	pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
-
-	regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
-	pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
+	u32 cfg;
+
+	cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
+
+	pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
+		(cfg & 0xff), (cfg >> 8) & 0xff,
+		BIT_ULL((cfg >> 16) & 0xff),
+		BIT_ULL((cfg >> 24) & 0xff));
+
+	cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
+	pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
 }
 
 static const struct of_device_id sifive_ccache_ids[] = {
-- 
2.17.1


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[PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

[Zong Li]

From: Ben Dooks <ben.dooks@sifive.com>

Use the pr_fmt() macro to prefix all the output with "CCACHE:"
to avoid having to write it out each time, or make a large diff
when the next change comes along.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 401c67a485e2..d749600c0bf8 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -5,6 +5,9 @@
  * Copyright (C) 2018-2022 SiFive, Inc.
  *
  */
+
+#define pr_fmt(fmt) "CCACHE: " fmt
+
 #include <linux/debugfs.h>
 #include <linux/interrupt.h>
 #include <linux/of_irq.h>
@@ -85,13 +88,13 @@ static void ccache_config_read(void)
 
 	cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
 
-	pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
+	pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
 		(cfg & 0xff), (cfg >> 8) & 0xff,
 		BIT_ULL((cfg >> 16) & 0xff),
 		BIT_ULL((cfg >> 24) & 0xff));
 
 	cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
-	pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
+	pr_info("Index of the largest way enabled: %d\n", cfg);
 }
 
 static const struct of_device_id sifive_ccache_ids[] = {
@@ -154,7 +157,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
 	if (irq == g_irq[DIR_CORR]) {
 		add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
 		add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
-		pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
+		pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DirError interrupt sig */
 		readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
 		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
@@ -172,7 +175,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
 	if (irq == g_irq[DATA_CORR]) {
 		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
 		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
-		pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
+		pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataError interrupt sig */
 		readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
 		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
@@ -181,7 +184,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
 	if (irq == g_irq[DATA_UNCORR]) {
 		add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
 		add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
-		pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
+		pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
 		/* Reading this register clears the DataFail interrupt sig */
 		readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
 		atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
@@ -221,7 +224,7 @@ static int __init sifive_ccache_init(void)
 		g_irq[i] = irq_of_parse_and_map(np, i);
 		rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
 		if (rc) {
-			pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
+			pr_err("Could not request IRQ %d\n", g_irq[i]);
 			return rc;
 		}
 	}
-- 
2.17.1


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[PATCH v2 6/6] EDAC/sifive: use sifive_ccache instead of sifive_l2

[Zong Li]

The sifive L2 has been renamed to sifive CCACHE, EDAC driver needs to
apply the change as well

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 drivers/edac/Kconfig       |  2 +-
 drivers/edac/sifive_edac.c | 12 ++++++------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 17562cf1fe97..456602d373b7 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -473,7 +473,7 @@ config EDAC_ALTERA_SDMMC
 
 config EDAC_SIFIVE
 	bool "Sifive platform EDAC driver"
-	depends on EDAC=y && SIFIVE_L2
+	depends on EDAC=y && SIFIVE_CCACHE
 	help
 	  Support for error detection and correction on the SiFive SoCs.
 
diff --git a/drivers/edac/sifive_edac.c b/drivers/edac/sifive_edac.c
index ee800aec7d47..b844e2626fd5 100644
--- a/drivers/edac/sifive_edac.c
+++ b/drivers/edac/sifive_edac.c
@@ -2,7 +2,7 @@
 /*
  * SiFive Platform EDAC Driver
  *
- * Copyright (C) 2018-2019 SiFive, Inc.
+ * Copyright (C) 2018-2022 SiFive, Inc.
  *
  * This driver is partially based on octeon_edac-pc.c
  *
@@ -10,7 +10,7 @@
 #include <linux/edac.h>
 #include <linux/platform_device.h>
 #include "edac_module.h"
-#include <soc/sifive/sifive_l2_cache.h>
+#include <soc/sifive/sifive_ccache.h>
 
 #define DRVNAME "sifive_edac"
 
@@ -32,9 +32,9 @@ int ecc_err_event(struct notifier_block *this, unsigned long event, void *ptr)
 
 	p = container_of(this, struct sifive_edac_priv, notifier);
 
-	if (event == SIFIVE_L2_ERR_TYPE_UE)
+	if (event == SIFIVE_CCACHE_ERR_TYPE_UE)
 		edac_device_handle_ue(p->dci, 0, 0, msg);
-	else if (event == SIFIVE_L2_ERR_TYPE_CE)
+	else if (event == SIFIVE_CCACHE_ERR_TYPE_CE)
 		edac_device_handle_ce(p->dci, 0, 0, msg);
 
 	return NOTIFY_OK;
@@ -67,7 +67,7 @@ static int ecc_register(struct platform_device *pdev)
 		goto err;
 	}
 
-	register_sifive_l2_error_notifier(&p->notifier);
+	register_sifive_ccache_error_notifier(&p->notifier);
 
 	return 0;
 
@@ -81,7 +81,7 @@ static int ecc_unregister(struct platform_device *pdev)
 {
 	struct sifive_edac_priv *p = platform_get_drvdata(pdev);
 
-	unregister_sifive_l2_error_notifier(&p->notifier);
+	unregister_sifive_ccache_error_notifier(&p->notifier);
 	edac_device_del_device(&pdev->dev);
 	edac_device_free_ctl_info(p->dci);
 
-- 
2.17.1


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Re: [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

[Conor.Dooley]

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Since composable cache may be L3 cache if private L2 cache exists, we
> should use its original name Composable cache to prevent confusion.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>

LGTM, thanks for fixing up the patch to actually show the move.
Not sure if the DT guys will want the move and the extra compatible
to be in extra patches, but to me it seems fair enough to do it all
in one go.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>  1 file changed, 23 insertions(+), 5 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> similarity index 83%
> rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> index ca3b9be58058..bf3f07421f7e 100644
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
> @@ -2,18 +2,18 @@
>  # Copyright (C) 2020 SiFive, Inc.
>  %YAML 1.2
>  ---
> -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
> +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
> 
> -title: SiFive L2 Cache Controller
> +title: SiFive Composable Cache Controller
> 
>  maintainers:
>    - Sagar Kadam <sagar.kadam@sifive.com>
>    - Paul Walmsley  <paul.walmsley@sifive.com>
> 
>  description:
> -  The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -  of memory for masters in a Core Complex. The Level 2 Cache Controller also
> +  The SiFive Composable Cache Controller is used to provide access to fast copies
> +  of memory for masters in a Core Complex. The Composable Cache Controller also
>    acts as directory-based coherency manager.
>    All the properties in ePAPR/DeviceTree specification applies for this platform.
> 
> @@ -22,6 +22,7 @@ select:
>      compatible:
>        contains:
>          enum:
> +          - sifive,ccache0
>            - sifive,fu540-c000-ccache
>            - sifive,fu740-c000-ccache
> 
> @@ -33,6 +34,7 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> +              - sifive,ccache0
>                - sifive,fu540-c000-ccache
>                - sifive,fu740-c000-ccache
>            - const: cache
> @@ -45,7 +47,7 @@ properties:
>      const: 64
> 
>    cache-level:
> -    const: 2
> +    enum: [2, 3]
> 
>    cache-sets:
>      enum: [1024, 2048]
> @@ -115,6 +117,22 @@ allOf:
>          cache-sets:
>            const: 1024
> 
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: sifive,ccache0
> +
> +    then:
> +      properties:
> +        cache-level:
> +          enum: [2, 3]
> +
> +    else:
> +      properties:
> +        cache-level:
> +          const: 2
> +
>  additionalProperties: false
> 
>  required:
> --
> 2.17.1
> 

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Conor.Dooley]

Hey Zong Li,
Couple comments on this patch.

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composable cache may be L3 cache if pL2 cache exists, we should use

What is a pL2 cache?

> its original name composable cache to prevent confusion.
> 
> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> table.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/soc/sifive/Kconfig                    |   6 +-
>  drivers/soc/sifive/Makefile                   |   2 +-
>  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>  4 files changed, 94 insertions(+), 93 deletions(-)
>  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)

If you're going to rename the header, you need to update all references to
it too, otherwise the other user (the EDAC) is going to have build issues,
i.e. patch 6 needs to get squashed into this one.


> diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
> similarity index 35%
> rename from drivers/soc/sifive/sifive_l2_cache.c
> rename to drivers/soc/sifive/sifive_ccache.c
> index 59640a1d0b28..1b16a196547f 100644
> --- a/drivers/soc/sifive/sifive_l2_cache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c

> -static const struct of_device_id sifive_l2_ids[] = {
> +static const struct of_device_id sifive_ccache_ids[] = {
>         { .compatible = "sifive,fu540-c000-ccache" },
>         { .compatible = "sifive,fu740-c000-ccache" },
> +       { .compatible = "sifive,ccache0" },
>         { /* end of table */ },

For v3, I think you should drop the , from the end of the table while
we are already editing it.
Thanks,
Conor.

>  };
> 

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Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts

[Conor.Dooley]

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Composable cache could be L2 or L3 cache, use 'cache-level' property of
> device node to determine the level.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  drivers/soc/sifive/sifive_ccache.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 1b16a196547f..0e0eb85c94d8 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -38,6 +38,7 @@
>  static void __iomem *ccache_base;
>  static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
>  static struct riscv_cacheinfo_ops ccache_cache_ops;
> +static int level;

Can you have a system with a composable l2 & l3 cache?

> 
>  enum {
>         DIR_CORR = 0,
> @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
>  static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
>  {
>         /* We want to use private group for composable cache only */
> -       if (this_leaf->level == 2)
> +       if (this_leaf->level == level)
>                 return &priv_attr_group;
>         else
>                 return NULL;
> @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
>         if (!ccache_base)
>                 return -ENOMEM;
> 
> +       if (of_property_read_u32(np, "cache-level", &level))
> +               return -ENODEV;
> +
>         intr_num = of_property_count_u32_elems(np, "interrupts");
>         if (!intr_num) {
>                 pr_err("CCACHE: no interrupts property\n");
> --
> 2.17.1
> 

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Re: [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init

[Conor.Dooley]

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Ben Dooks <ben.dooks@sifive.com>
> 
> The driver prints out 6 lines on startup, which can easily be redcued
> to two lines without losing any information.
> 
> Note, to make the types work better, uint64_t has been replaced with
> ULL to make the unsigned long long match the format in the print
> statement.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>

Hey Zong,
Missing your SoB after Ben's here btw.

> ---
>  drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
>  1 file changed, 11 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 0e0eb85c94d8..401c67a485e2 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
> 
>  static void ccache_config_read(void)
>  {
> -       u32 regval, val;
> -
> -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> -       val = regval & 0xFF;
> -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> -       val = (regval & 0xFF00) >> 8;
> -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> -       val = (regval & 0xFF0000) >> 16;
> -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> -       val = (regval & 0xFF000000) >> 24;
> -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> -
> -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> +       u32 cfg;
> +
> +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> +
> +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> +               (cfg & 0xff), (cfg >> 8) & 0xff,
> +               BIT_ULL((cfg >> 16) & 0xff),
> +               BIT_ULL((cfg >> 24) & 0xff));

Could we use defines please for the register shifts please?

> +
> +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);

%u here no?
Thanks,
Conor.

>  }
> 
>  static const struct of_device_id sifive_ccache_ids[] = {
> --
> 2.17.1
> 

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Re: [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

[Conor.Dooley]

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Ben Dooks <ben.dooks@sifive.com>
> 
> Use the pr_fmt() macro to prefix all the output with "CCACHE:"
> to avoid having to write it out each time, or make a large diff
> when the next change comes along.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>

Missing your SoB again here Zong Li btw, other than that:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> ---
>  drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> index 401c67a485e2..d749600c0bf8 100644
> --- a/drivers/soc/sifive/sifive_ccache.c
> +++ b/drivers/soc/sifive/sifive_ccache.c
> @@ -5,6 +5,9 @@
>   * Copyright (C) 2018-2022 SiFive, Inc.
>   *
>   */
> +
> +#define pr_fmt(fmt) "CCACHE: " fmt
> +
>  #include <linux/debugfs.h>
>  #include <linux/interrupt.h>
>  #include <linux/of_irq.h>
> @@ -85,13 +88,13 @@ static void ccache_config_read(void)
> 
>         cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> 
> -       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> +       pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
>                 (cfg & 0xff), (cfg >> 8) & 0xff,
>                 BIT_ULL((cfg >> 16) & 0xff),
>                 BIT_ULL((cfg >> 24) & 0xff));
> 
>         cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> -       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> +       pr_info("Index of the largest way enabled: %d\n", cfg);
>  }
> 
>  static const struct of_device_id sifive_ccache_ids[] = {
> @@ -154,7 +157,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
>         if (irq == g_irq[DIR_CORR]) {
>                 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
>                 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
> -               pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> +               pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
>                 /* Reading this register clears the DirError interrupt sig */
>                 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
>                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> @@ -172,7 +175,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
>         if (irq == g_irq[DATA_CORR]) {
>                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
>                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
> -               pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> +               pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
>                 /* Reading this register clears the DataError interrupt sig */
>                 readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
>                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> @@ -181,7 +184,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
>         if (irq == g_irq[DATA_UNCORR]) {
>                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
>                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
> -               pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> +               pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
>                 /* Reading this register clears the DataFail interrupt sig */
>                 readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
>                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
> @@ -221,7 +224,7 @@ static int __init sifive_ccache_init(void)
>                 g_irq[i] = irq_of_parse_and_map(np, i);
>                 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
>                 if (rc) {
> -                       pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
> +                       pr_err("Could not request IRQ %d\n", g_irq[i]);
>                         return rc;
>                 }
>         }
> --
> 2.17.1
> 

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Conor.Dooley]

Noticed a another thing, sorry..

On 05/09/2022 09:31, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Since composable cache may be L3 cache if pL2 cache exists, we should use
> its original name composable cache to prevent confusion.
> 
> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> table.
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>  drivers/soc/sifive/Kconfig                    |   6 +-
>  drivers/soc/sifive/Makefile                   |   2 +-
>  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>  4 files changed, 94 insertions(+), 93 deletions(-)
>  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> 

> -static ssize_t l2_write(struct file *file, const char __user *data,
> +static ssize_t ccache_write(struct file *file, const char __user *data,
>                         size_t count, loff_t *ppos)

You need to fix the alignment here as per checkpatch:
CHECK: Alignment should match open parenthesis
#112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
+static ssize_t ccache_write(struct file *file, const char __user *data,
+                       size_t count, loff_t *ppos)

>  {
>         unsigned int val;
> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>         if (kstrtouint_from_user(data, count, 0, &val))
>                 return -EINVAL;
>         if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>         else
>                 return -EINVAL;
>         return count;
>  }
> 
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Re: [PATCH v2 5/6] soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:47寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Ben Dooks <ben.dooks@sifive.com>
> >
> > Use the pr_fmt() macro to prefix all the output with "CCACHE:"
> > to avoid having to write it out each time, or make a large diff
> > when the next change comes along.
> >
> > Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>
> Missing your SoB again here Zong Li btw, other than that:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks, I would add it in V3.

>
> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 15 +++++++++------
> >  1 file changed, 9 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 401c67a485e2..d749600c0bf8 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -5,6 +5,9 @@
> >   * Copyright (C) 2018-2022 SiFive, Inc.
> >   *
> >   */
> > +
> > +#define pr_fmt(fmt) "CCACHE: " fmt
> > +
> >  #include <linux/debugfs.h>
> >  #include <linux/interrupt.h>
> >  #include <linux/of_irq.h>
> > @@ -85,13 +88,13 @@ static void ccache_config_read(void)
> >
> >         cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> >
> > -       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> > +       pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> >                 (cfg & 0xff), (cfg >> 8) & 0xff,
> >                 BIT_ULL((cfg >> 16) & 0xff),
> >                 BIT_ULL((cfg >> 24) & 0xff));
> >
> >         cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > -       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
> > +       pr_info("Index of the largest way enabled: %d\n", cfg);
> >  }
> >
> >  static const struct of_device_id sifive_ccache_ids[] = {
> > @@ -154,7 +157,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> >         if (irq == g_irq[DIR_CORR]) {
> >                 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH);
> >                 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW);
> > -               pr_err("CCACHE: DirError @ 0x%08X.%08X\n", add_h, add_l);
> > +               pr_err("DirError @ 0x%08X.%08X\n", add_h, add_l);
> >                 /* Reading this register clears the DirError interrupt sig */
> >                 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT);
> >                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> > @@ -172,7 +175,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> >         if (irq == g_irq[DATA_CORR]) {
> >                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_HIGH);
> >                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_LOW);
> > -               pr_err("CCACHE: DataError @ 0x%08X.%08X\n", add_h, add_l);
> > +               pr_err("DataError @ 0x%08X.%08X\n", add_h, add_l);
> >                 /* Reading this register clears the DataError interrupt sig */
> >                 readl(ccache_base + SIFIVE_CCACHE_DATECCFIX_COUNT);
> >                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_CE,
> > @@ -181,7 +184,7 @@ static irqreturn_t ccache_int_handler(int irq, void *device)
> >         if (irq == g_irq[DATA_UNCORR]) {
> >                 add_h = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_HIGH);
> >                 add_l = readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_LOW);
> > -               pr_err("CCACHE: DataFail @ 0x%08X.%08X\n", add_h, add_l);
> > +               pr_err("DataFail @ 0x%08X.%08X\n", add_h, add_l);
> >                 /* Reading this register clears the DataFail interrupt sig */
> >                 readl(ccache_base + SIFIVE_CCACHE_DATECCFAIL_COUNT);
> >                 atomic_notifier_call_chain(&ccache_err_chain, SIFIVE_CCACHE_ERR_TYPE_UE,
> > @@ -221,7 +224,7 @@ static int __init sifive_ccache_init(void)
> >                 g_irq[i] = irq_of_parse_and_map(np, i);
> >                 rc = request_irq(g_irq[i], ccache_int_handler, 0, "ccache_ecc", NULL);
> >                 if (rc) {
> > -                       pr_err("CCACHE: Could not request IRQ %d\n", g_irq[i]);
> > +                       pr_err("Could not request IRQ %d\n", g_irq[i]);
> >                         return rc;
> >                 }
> >         }
> > --
> > 2.17.1
> >
>

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Re: [PATCH v2 4/6] soc: sifive: ccache: reduce printing on init

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨3:18寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Ben Dooks <ben.dooks@sifive.com>
> >
> > The driver prints out 6 lines on startup, which can easily be redcued
> > to two lines without losing any information.
> >
> > Note, to make the types work better, uint64_t has been replaced with
> > ULL to make the unsigned long long match the format in the print
> > statement.
> >
> > Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
>
> Hey Zong,
> Missing your SoB after Ben's here btw.
>

Ok, I would add it in V3.

> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >  1 file changed, 11 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 0e0eb85c94d8..401c67a485e2 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
> >
> >  static void ccache_config_read(void)
> >  {
> > -       u32 regval, val;
> > -
> > -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> > -       val = regval & 0xFF;
> > -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> > -       val = (regval & 0xFF00) >> 8;
> > -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> > -       val = (regval & 0xFF0000) >> 16;
> > -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> > -       val = (regval & 0xFF000000) >> 24;
> > -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> > -
> > -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> > +       u32 cfg;
> > +
> > +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> > +
> > +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> > +               (cfg & 0xff), (cfg >> 8) & 0xff,
> > +               BIT_ULL((cfg >> 16) & 0xff),
> > +               BIT_ULL((cfg >> 24) & 0xff));
>
> Could we use defines please for the register shifts please?
>

Yes, let me define them in V3

> > +
> > +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>
> %u here no?

Thanks for point it out. I would change it in V3.

> Thanks,
> Conor.
>
> >  }
> >
> >  static const struct of_device_id sifive_ccache_ids[] = {
> > --
> > 2.17.1
> >
>

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
>
> Noticed a another thing, sorry..
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > Since composable cache may be L3 cache if pL2 cache exists, we should use
> > its original name composable cache to prevent confusion.
> >
> > Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> > table.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  drivers/soc/sifive/Kconfig                    |   6 +-
> >  drivers/soc/sifive/Makefile                   |   2 +-
> >  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >  4 files changed, 94 insertions(+), 93 deletions(-)
> >  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> >
>
> > -static ssize_t l2_write(struct file *file, const char __user *data,
> > +static ssize_t ccache_write(struct file *file, const char __user *data,
> >                         size_t count, loff_t *ppos)
>
> You need to fix the alignment here as per checkpatch:
> CHECK: Alignment should match open parenthesis
> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
> +static ssize_t ccache_write(struct file *file, const char __user *data,
> +                       size_t count, loff_t *ppos)
>

I'm not sure why I don't see that by checkpatch, but it looks that it
is actually misalignment there, I would re-check all indents in
source. Thanks.

> >  {
> >         unsigned int val;
> > @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
> >         if (kstrtouint_from_user(data, count, 0, &val))
> >                 return -EINVAL;
> >         if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> > -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> > +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> >         else
> >                 return -EINVAL;
> >         return count;
> >  }
> >

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:46寫道：
>
> Hey Zong Li,
> Couple comments on this patch.
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Greentime Hu <greentime.hu@sifive.com>
> >
> > Since composable cache may be L3 cache if pL2 cache exists, we should use
>
> What is a pL2 cache?

The pL2 is stand for private L2 cache, it is a L2 cache in our system.
Perhaps I should change the pL2 to L2 in the description for more
generic.

>
> > its original name composable cache to prevent confusion.
> >
> > Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> > table.
> >
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  drivers/soc/sifive/Kconfig                    |   6 +-
> >  drivers/soc/sifive/Makefile                   |   2 +-
> >  .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >  .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >  4 files changed, 94 insertions(+), 93 deletions(-)
> >  rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >  rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>
> If you're going to rename the header, you need to update all references to
> it too, otherwise the other user (the EDAC) is going to have build issues,
> i.e. patch 6 needs to get squashed into this one.
>

Ok, let me merge these two patches, as you mentioned, we probably
don't want to see the build is broken in git bisect as well.

>
> > diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_ccache.c
> > similarity index 35%
> > rename from drivers/soc/sifive/sifive_l2_cache.c
> > rename to drivers/soc/sifive/sifive_ccache.c
> > index 59640a1d0b28..1b16a196547f 100644
> > --- a/drivers/soc/sifive/sifive_l2_cache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
>
> > -static const struct of_device_id sifive_l2_ids[] = {
> > +static const struct of_device_id sifive_ccache_ids[] = {
> >         { .compatible = "sifive,fu540-c000-ccache" },
> >         { .compatible = "sifive,fu740-c000-ccache" },
> > +       { .compatible = "sifive,ccache0" },
> >         { /* end of table */ },
>
> For v3, I think you should drop the , from the end of the table while
> we are already editing it.

Thanks, I will remove it.

> Thanks,
> Conor.
>
> >  };
> >
>

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Re: [PATCH v2 3/6] soc: sifive: ccache: determine the cache level from dts

[Zong Li]

<Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:56寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Composable cache could be L2 or L3 cache, use 'cache-level' property of
> > device node to determine the level.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 1b16a196547f..0e0eb85c94d8 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -38,6 +38,7 @@
> >  static void __iomem *ccache_base;
> >  static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR];
> >  static struct riscv_cacheinfo_ops ccache_cache_ops;
> > +static int level;
>
> Can you have a system with a composable l2 & l3 cache?

We don't have a system with composable L2 and L3 cache at same time.
But as I mentioned in the thread of second patch, we use another cache
as L2 when the composable cache used for L3.

>
> >
> >  enum {
> >         DIR_CORR = 0,
> > @@ -143,7 +144,7 @@ static const struct attribute_group priv_attr_group = {
> >  static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf)
> >  {
> >         /* We want to use private group for composable cache only */
> > -       if (this_leaf->level == 2)
> > +       if (this_leaf->level == level)
> >                 return &priv_attr_group;
> >         else
> >                 return NULL;
> > @@ -210,6 +211,9 @@ static int __init sifive_ccache_init(void)
> >         if (!ccache_base)
> >                 return -ENOMEM;
> >
> > +       if (of_property_read_u32(np, "cache-level", &level))
> > +               return -ENODEV;
> > +
> >         intr_num = of_property_count_u32_elems(np, "interrupts");
> >         if (!intr_num) {
> >                 pr_err("CCACHE: no interrupts property\n");
> > --
> > 2.17.1
> >
>

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Conor.Dooley]

On 06/09/2022 02:44, Zong Li wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
>>
>> Noticed a another thing, sorry..
>>
>> On 05/09/2022 09:31, Zong Li wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Greentime Hu <greentime.hu@sifive.com>
>>>
>>> Since composable cache may be L3 cache if pL2 cache exists, we should use
>>> its original name composable cache to prevent confusion.
>>>
>>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
>>> table.
>>>
>>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>>> Signed-off-by: Zong Li <zong.li@sifive.com>
>>> ---
>>>   drivers/soc/sifive/Kconfig                    |   6 +-
>>>   drivers/soc/sifive/Makefile                   |   2 +-
>>>   .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
>>>   .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
>>>   4 files changed, 94 insertions(+), 93 deletions(-)
>>>   rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
>>>   rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
>>>
>>
>>> -static ssize_t l2_write(struct file *file, const char __user *data,
>>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>>>                          size_t count, loff_t *ppos)
>>
>> You need to fix the alignment here as per checkpatch:
>> CHECK: Alignment should match open parenthesis
>> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
>> +static ssize_t ccache_write(struct file *file, const char __user *data,
>> +                       size_t count, loff_t *ppos)
>>
> 
> I'm not sure why I don't see that by checkpatch, but it looks that it
> is actually misalignment there, I would re-check all indents in
> source. Thanks.

You need to pass --strict to checkpatch to see it.

> 
>>>   {
>>>          unsigned int val;
>>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
>>>          if (kstrtouint_from_user(data, count, 0, &val))
>>>                  return -EINVAL;
>>>          if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
>>> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
>>> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
>>>          else
>>>                  return -EINVAL;
>>>          return count;
>>>   }
>>>

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Re: [PATCH v2 2/6] soc: sifive: ccache: Rename SiFive L2 cache to Composable cache.

[Zong Li]

On Tue, Sep 6, 2022 at 2:23 PM <Conor.Dooley@microchip.com> wrote:
>
> On 06/09/2022 02:44, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > <Conor.Dooley@microchip.com> 於 2022年9月6日 週二 凌晨2:48寫道：
> >>
> >> Noticed a another thing, sorry..
> >>
> >> On 05/09/2022 09:31, Zong Li wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>> From: Greentime Hu <greentime.hu@sifive.com>
> >>>
> >>> Since composable cache may be L3 cache if pL2 cache exists, we should use
> >>> its original name composable cache to prevent confusion.
> >>>
> >>> Apart from renaming, we also add the compatible "sifive,ccache0" into ID
> >>> table.
> >>>
> >>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> >>> Signed-off-by: Zong Li <zong.li@sifive.com>
> >>> ---
> >>>   drivers/soc/sifive/Kconfig                    |   6 +-
> >>>   drivers/soc/sifive/Makefile                   |   2 +-
> >>>   .../{sifive_l2_cache.c => sifive_ccache.c}    | 163 +++++++++---------
> >>>   .../{sifive_l2_cache.h => sifive_ccache.h}    |  16 +-
> >>>   4 files changed, 94 insertions(+), 93 deletions(-)
> >>>   rename drivers/soc/sifive/{sifive_l2_cache.c => sifive_ccache.c} (35%)
> >>>   rename include/soc/sifive/{sifive_l2_cache.h => sifive_ccache.h} (12%)
> >>>
> >>
> >>> -static ssize_t l2_write(struct file *file, const char __user *data,
> >>> +static ssize_t ccache_write(struct file *file, const char __user *data,
> >>>                          size_t count, loff_t *ppos)
> >>
> >> You need to fix the alignment here as per checkpatch:
> >> CHECK: Alignment should match open parenthesis
> >> #112: FILE: drivers/soc/sifive/sifive_ccache.c:53:
> >> +static ssize_t ccache_write(struct file *file, const char __user *data,
> >> +                       size_t count, loff_t *ppos)
> >>
> >
> > I'm not sure why I don't see that by checkpatch, but it looks that it
> > is actually misalignment there, I would re-check all indents in
> > source. Thanks.
>
> You need to pass --strict to checkpatch to see it.

Many thanks for the tip, I can see the message after applying the option.

>
> >
> >>>   {
> >>>          unsigned int val;
> >>> @@ -57,75 +57,76 @@ static ssize_t l2_write(struct file *file, const char __user *data,
> >>>          if (kstrtouint_from_user(data, count, 0, &val))
> >>>                  return -EINVAL;
> >>>          if ((val < 0xFF) || (val >= 0x10000 && val < 0x100FF))
> >>> -               writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
> >>> +               writel(val, ccache_base + SIFIVE_CCACHE_ECCINJECTERR);
> >>>          else
> >>>                  return -EINVAL;
> >>>          return count;
> >>>   }
> >>>
>

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Re: [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

[Rob Herring]

On Mon, 05 Sep 2022 08:31:20 +0000, Zong Li wrote:
> Since composable cache may be L3 cache if private L2 cache exists, we
> should use its original name Composable cache to prevent confusion.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
> ---
>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>  1 file changed, 23 insertions(+), 5 deletions(-)
>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

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Re: [PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

[Conor.Dooley]

On 08/09/2022 22:21, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 05 Sep 2022 08:31:20 +0000, Zong Li wrote:
>> Since composable cache may be L3 cache if private L2 cache exists, we
>> should use its original name Composable cache to prevent confusion.
>>
>> Signed-off-by: Zong Li <zong.li@sifive.com>
>> Suggested-by: Conor Dooley <conor.dooley@microchip.com>
>> Suggested-by: Ben Dooks <ben.dooks@sifive.com>
>> ---
>>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>>  1 file changed, 23 insertions(+), 5 deletions(-)
>>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
>>
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

FWIW this was respun today:
https://lore.kernel.org/linux-riscv/20220908144424.4232-1-zong.li@sifive.com/

Content of this patch should be no different.
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