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* [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest
@ 2022-09-06 14:58 Andrew Jones
  2022-09-06 14:58 ` [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size Andrew Jones
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Andrew Jones @ 2022-09-06 14:58 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv; +Cc: Anup Patel, Atish Patra

Add support for exposing the Zicbom extension to guests. This has been
tested over a QEMU including the Zicbom support [1] ([1] was rebased and
the Zicboz support from it was dropped.) QEMU was further modified to
ensure the cache block size was provided in the DT. kvmtool was also
modified [2] to test the new KVM API and provide the guest the cache
block size in its DT (The kvmtool patches are based on Anup's Svpbmt/Sstc
series [3]). These KVM patches are based on the riscv_init_cbom_blocksize()
cleanup patch from Palmer and the move and expose riscv_cbom_block_size
patch from Anup which was reposted [4]. This series is also available here
[5].

[1] https://gitlab.com/jones-drew/qemu/-/commits/riscv/zicbom
[2] https://github.com/jones-drew/kvmtool/commits/riscv/zicbom
[3] https://github.com/avpatel/kvmtool/commits/riscv_svpbmt_sstc_v1
[4] https://lore.kernel.org/linux-riscv/20220906074509.928865-1-ajones@ventanamicro.com/T/#u
[5] https://github.com/jones-drew/linux/commits/riscv/kvm/zicbom-v2

Thanks,
drew

v2:
 - Dropped a patch that output the cache block size to dmesg

Andrew Jones (2):
  RISC-V: KVM: Provide UAPI for Zicbom block size
  RISC-V: KVM: Expose Zicbom to the guest

 arch/riscv/include/uapi/asm/kvm.h |  2 ++
 arch/riscv/kvm/vcpu.c             | 11 +++++++++++
 arch/riscv/mm/cacheflush.c        |  1 +
 3 files changed, 14 insertions(+)

-- 
2.37.2


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^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size
  2022-09-06 14:58 [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest Andrew Jones
@ 2022-09-06 14:58 ` Andrew Jones
       [not found]   ` <CAOnJCUJDoAiDhavwisxj4QVGruTb67STb_WqQ5NuojzDwLLqng@mail.gmail.com>
  2022-09-06 14:58 ` [PATCH v2 2/2] RISC-V: KVM: Expose Zicbom to the guest Andrew Jones
  2022-09-06 16:10 ` [PATCH v2 0/2] riscv: " Conor.Dooley
  2 siblings, 1 reply; 6+ messages in thread
From: Andrew Jones @ 2022-09-06 14:58 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv; +Cc: Anup Patel, Atish Patra

We're about to allow guests to use the Zicbom extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 6 ++++++
 arch/riscv/mm/cacheflush.c        | 1 +
 3 files changed, 8 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 7351417afd62..b9a4cf36be4b 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -48,6 +48,7 @@ struct kvm_sregs {
 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 struct kvm_riscv_config {
 	unsigned long isa;
+	unsigned long zicbom_block_size;
 };
 
 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index d0f08d5b4282..3f36e79876e7 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -18,6 +18,7 @@
 #include <linux/fs.h>
 #include <linux/kvm_host.h>
 #include <asm/csr.h>
+#include <asm/cacheflush.h>
 #include <asm/hwcap.h>
 
 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
@@ -254,6 +255,9 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
 	case KVM_REG_RISCV_CONFIG_REG(isa):
 		reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
 		break;
+	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
+		reg_val = riscv_cbom_block_size;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -311,6 +315,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 			return -EOPNOTSUPP;
 		}
 		break;
+	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
+		return -EOPNOTSUPP;
 	default:
 		return -EINVAL;
 	}
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index e5b087be1577..f318b2553612 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -90,6 +90,7 @@ void flush_icache_pte(pte_t pte)
 #endif /* CONFIG_MMU */
 
 unsigned int riscv_cbom_block_size;
+EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
 
 #ifdef CONFIG_RISCV_ISA_ZICBOM
 void riscv_init_cbom_blocksize(void)
-- 
2.37.2


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^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v2 2/2] RISC-V: KVM: Expose Zicbom to the guest
  2022-09-06 14:58 [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest Andrew Jones
  2022-09-06 14:58 ` [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size Andrew Jones
@ 2022-09-06 14:58 ` Andrew Jones
  2022-09-06 16:10 ` [PATCH v2 0/2] riscv: " Conor.Dooley
  2 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2022-09-06 14:58 UTC (permalink / raw)
  To: kvm-riscv, linux-riscv; +Cc: Anup Patel, Atish Patra

Guests may use the cbo.inval,clean,flush instructions when the
CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
(for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).

Add Zicbom support for KVM guests which may be enabled and
disabled from KVM userspace using the ISA extension ONE_REG API.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b9a4cf36be4b..ed37a4a6e5cf 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_M,
 	KVM_RISCV_ISA_EXT_SVPBMT,
 	KVM_RISCV_ISA_EXT_SSTC,
+	KVM_RISCV_ISA_EXT_ZICBOM,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 3f36e79876e7..3ce4f1c11b4c 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	RISCV_ISA_EXT_m,
 	RISCV_ISA_EXT_SVPBMT,
 	RISCV_ISA_EXT_SSTC,
+	RISCV_ISA_EXT_ZICBOM,
 };
 
 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -795,6 +796,10 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
 
 	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC))
 		henvcfg |= ENVCFG_STCE;
+
+	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_ZICBOM))
+		henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
+
 	csr_write(CSR_HENVCFG, henvcfg);
 #ifdef CONFIG_32BIT
 	csr_write(CSR_HENVCFGH, henvcfg >> 32);
-- 
2.37.2


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^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest
  2022-09-06 14:58 [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest Andrew Jones
  2022-09-06 14:58 ` [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size Andrew Jones
  2022-09-06 14:58 ` [PATCH v2 2/2] RISC-V: KVM: Expose Zicbom to the guest Andrew Jones
@ 2022-09-06 16:10 ` Conor.Dooley
  2 siblings, 0 replies; 6+ messages in thread
From: Conor.Dooley @ 2022-09-06 16:10 UTC (permalink / raw)
  To: ajones, kvm-riscv, linux-riscv; +Cc: anup, atishp

On 06/09/2022 15:58, Andrew Jones wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add support for exposing the Zicbom extension to guests. This has been
> tested over a QEMU including the Zicbom support [1] ([1] was rebased and
> the Zicboz support from it was dropped.) QEMU was further modified to
> ensure the cache block size was provided in the DT. kvmtool was also
> modified [2] to test the new KVM API and provide the guest the cache
> block size in its DT (The kvmtool patches are based on Anup's Svpbmt/Sstc
> series [3]). These KVM patches are based on the riscv_init_cbom_blocksize()
> cleanup patch from Palmer and the move and expose riscv_cbom_block_size
> patch from Anup which was reposted [4]. This series is also available here
> [5].

Saw this right before I left it against v1, but both of these patches
look sane-&-reasonable to me.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

> 
> [1] https://gitlab.com/jones-drew/qemu/-/commits/riscv/zicbom
> [2] https://github.com/jones-drew/kvmtool/commits/riscv/zicbom
> [3] https://github.com/avpatel/kvmtool/commits/riscv_svpbmt_sstc_v1
> [4] https://lore.kernel.org/linux-riscv/20220906074509.928865-1-ajones@ventanamicro.com/T/#u
> [5] https://github.com/jones-drew/linux/commits/riscv/kvm/zicbom-v2
> 
> Thanks,
> drew
> 
> v2:
>  - Dropped a patch that output the cache block size to dmesg
> 
> Andrew Jones (2):
>   RISC-V: KVM: Provide UAPI for Zicbom block size
>   RISC-V: KVM: Expose Zicbom to the guest
> 
>  arch/riscv/include/uapi/asm/kvm.h |  2 ++
>  arch/riscv/kvm/vcpu.c             | 11 +++++++++++
>  arch/riscv/mm/cacheflush.c        |  1 +
>  3 files changed, 14 insertions(+)
> 
> --
> 2.37.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size
       [not found]   ` <CAOnJCUJDoAiDhavwisxj4QVGruTb67STb_WqQ5NuojzDwLLqng@mail.gmail.com>
@ 2022-09-08  2:54     ` Anup Patel
  2022-09-08  7:43       ` Andrew Jones
  0 siblings, 1 reply; 6+ messages in thread
From: Anup Patel @ 2022-09-08  2:54 UTC (permalink / raw)
  To: Atish Patra; +Cc: Andrew Jones, kvm-riscv, linux-riscv

On Thu, Sep 8, 2022 at 4:19 AM Atish Patra <atishp@atishpatra.org> wrote:
>
>
>
> On Tue, Sep 6, 2022 at 7:58 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>>
>> We're about to allow guests to use the Zicbom extension. KVM
>> userspace needs to know the cache block size in order to
>> properly advertise it to the guest. Provide a virtual config
>> register for userspace to get it with the GET_ONE_REG API, but
>> setting it cannot be supported, so disallow SET_ONE_REG.
>>
>> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
>> ---
>>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>>  arch/riscv/kvm/vcpu.c             | 6 ++++++
>>  arch/riscv/mm/cacheflush.c        | 1 +
>>  3 files changed, 8 insertions(+)
>>
>> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
>> index 7351417afd62..b9a4cf36be4b 100644
>> --- a/arch/riscv/include/uapi/asm/kvm.h
>> +++ b/arch/riscv/include/uapi/asm/kvm.h
>> @@ -48,6 +48,7 @@ struct kvm_sregs {
>>  /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
>>  struct kvm_riscv_config {
>>         unsigned long isa;
>> +       unsigned long zicbom_block_size;
>>  };
>>
>>  /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
>> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
>> index d0f08d5b4282..3f36e79876e7 100644
>> --- a/arch/riscv/kvm/vcpu.c
>> +++ b/arch/riscv/kvm/vcpu.c
>> @@ -18,6 +18,7 @@
>>  #include <linux/fs.h>
>>  #include <linux/kvm_host.h>
>>  #include <asm/csr.h>
>> +#include <asm/cacheflush.h>
>>  #include <asm/hwcap.h>
>>
>>  const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
>> @@ -254,6 +255,9 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
>>         case KVM_REG_RISCV_CONFIG_REG(isa):
>>                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
>>                 break;
>> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
>> +               reg_val = riscv_cbom_block_size;
>> +               break;
>
>
> Don't we need CONFIG_RISCV_ISA_ZICBOM here ? This one reg interface should only return riscv_cbom_block_size if we enable the parsing. Isn't it ?

The riscv_cbom_block_size is in the wrong location. This global variable
should always be available irrespective CONFIG_RISCV_ISA_ZICBOM
is enabled or not.

Better to check ISA feature flag instead of CONFIG_RISCV_ISA_ZICBOM.

Regards,
Anup

>
>>
>>         default:
>>                 return -EINVAL;
>>         }
>> @@ -311,6 +315,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
>>                         return -EOPNOTSUPP;
>>                 }
>>                 break;
>> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
>> +               return -EOPNOTSUPP;
>>         default:
>>                 return -EINVAL;
>>         }
>> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
>> index e5b087be1577..f318b2553612 100644
>> --- a/arch/riscv/mm/cacheflush.c
>> +++ b/arch/riscv/mm/cacheflush.c
>> @@ -90,6 +90,7 @@ void flush_icache_pte(pte_t pte)
>>  #endif /* CONFIG_MMU */
>>
>>  unsigned int riscv_cbom_block_size;
>> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
>>
>>  #ifdef CONFIG_RISCV_ISA_ZICBOM
>>  void riscv_init_cbom_blocksize(void)
>> --
>> 2.37.2
>>
>
>
> --
> Regards,
> Atish

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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size
  2022-09-08  2:54     ` Anup Patel
@ 2022-09-08  7:43       ` Andrew Jones
  0 siblings, 0 replies; 6+ messages in thread
From: Andrew Jones @ 2022-09-08  7:43 UTC (permalink / raw)
  To: Anup Patel; +Cc: Atish Patra, kvm-riscv, linux-riscv

On Thu, Sep 08, 2022 at 08:24:32AM +0530, Anup Patel wrote:
> On Thu, Sep 8, 2022 at 4:19 AM Atish Patra <atishp@atishpatra.org> wrote:
> >
> >
> >
> > On Tue, Sep 6, 2022 at 7:58 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> >>
> >> We're about to allow guests to use the Zicbom extension. KVM
> >> userspace needs to know the cache block size in order to
> >> properly advertise it to the guest. Provide a virtual config
> >> register for userspace to get it with the GET_ONE_REG API, but
> >> setting it cannot be supported, so disallow SET_ONE_REG.
> >>
> >> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> >> ---
> >>  arch/riscv/include/uapi/asm/kvm.h | 1 +
> >>  arch/riscv/kvm/vcpu.c             | 6 ++++++
> >>  arch/riscv/mm/cacheflush.c        | 1 +
> >>  3 files changed, 8 insertions(+)
> >>
> >> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> >> index 7351417afd62..b9a4cf36be4b 100644
> >> --- a/arch/riscv/include/uapi/asm/kvm.h
> >> +++ b/arch/riscv/include/uapi/asm/kvm.h
> >> @@ -48,6 +48,7 @@ struct kvm_sregs {
> >>  /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> >>  struct kvm_riscv_config {
> >>         unsigned long isa;
> >> +       unsigned long zicbom_block_size;
> >>  };
> >>
> >>  /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> >> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> >> index d0f08d5b4282..3f36e79876e7 100644
> >> --- a/arch/riscv/kvm/vcpu.c
> >> +++ b/arch/riscv/kvm/vcpu.c
> >> @@ -18,6 +18,7 @@
> >>  #include <linux/fs.h>
> >>  #include <linux/kvm_host.h>
> >>  #include <asm/csr.h>
> >> +#include <asm/cacheflush.h>
> >>  #include <asm/hwcap.h>
> >>
> >>  const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
> >> @@ -254,6 +255,9 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> >>         case KVM_REG_RISCV_CONFIG_REG(isa):
> >>                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
> >>                 break;
> >> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> >> +               reg_val = riscv_cbom_block_size;
> >> +               break;
> >
> >
> > Don't we need CONFIG_RISCV_ISA_ZICBOM here ? This one reg interface should only return riscv_cbom_block_size if we enable the parsing. Isn't it ?
> 
> The riscv_cbom_block_size is in the wrong location. This global variable
> should always be available irrespective CONFIG_RISCV_ISA_ZICBOM
> is enabled or not.

Just to clarify, riscv_cbom_block_size *was* in the wrong location, but
after Anup's move patch, which this patch is based on, it's in the right
location.

> 
> Better to check ISA feature flag instead of CONFIG_RISCV_ISA_ZICBOM.

Good suggestion. It does seem reasonable that reading a virtual register,
which is dependent on an ISA feature, should return EINVAL when the ISA
feature isn't present. If that isn't yet documented somewhere, then I'll
add it to my TODO list to document it as well, but I'm not sure we want
to hold up this patch on a documentation patch. For now I'll just spin a
v3 which adds the check.

Thanks,
drew

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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-09-08  7:43 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-06 14:58 [PATCH v2 0/2] riscv: KVM: Expose Zicbom to the guest Andrew Jones
2022-09-06 14:58 ` [PATCH v2 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size Andrew Jones
     [not found]   ` <CAOnJCUJDoAiDhavwisxj4QVGruTb67STb_WqQ5NuojzDwLLqng@mail.gmail.com>
2022-09-08  2:54     ` Anup Patel
2022-09-08  7:43       ` Andrew Jones
2022-09-06 14:58 ` [PATCH v2 2/2] RISC-V: KVM: Expose Zicbom to the guest Andrew Jones
2022-09-06 16:10 ` [PATCH v2 0/2] riscv: " Conor.Dooley

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