From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com, "Andy Chiu" <andy.chiu@sifive.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Heiko Stuebner" <heiko.stuebner@vrull.eu>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Liao Chang" <liaochang1@huawei.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Vincent Chen" <vincent.chen@sifive.com>,
"Guo Ren" <guoren@kernel.org>, "Björn Töpel" <bjorn@rivosinc.com>,
"Xianting Tian" <xianting.tian@linux.alibaba.com>,
"Mattias Nissler" <mnissler@rivosinc.com>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap
Date: Fri, 17 Mar 2023 11:35:29 +0000 [thread overview]
Message-ID: <20230317113538.10878-11-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com>
Vector unit is disabled by default for all user processes. Thus, a
process will take a trap (illegal instruction) into kernel at the first
time when it uses Vector. Only after then, the kernel allocates V
context and starts take care of the context for that user process.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
arch/riscv/include/asm/insn.h | 29 +++++++++++
arch/riscv/include/asm/vector.h | 2 +
arch/riscv/kernel/traps.c | 14 ++++-
arch/riscv/kernel/vector.c | 90 +++++++++++++++++++++++++++++++++
4 files changed, 133 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 8d5c84f2d5ef..4e1505cef8aa 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -137,6 +137,26 @@
#define RVG_OPCODE_JALR 0x67
#define RVG_OPCODE_JAL 0x6f
#define RVG_OPCODE_SYSTEM 0x73
+#define RVG_SYSTEM_CSR_OFF 20
+#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
+
+/* parts of opcode for RVF, RVD and RVQ */
+#define RVFDQ_FL_FS_WIDTH_OFF 12
+#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0)
+#define RVFDQ_FL_FS_WIDTH_W 2
+#define RVFDQ_FL_FS_WIDTH_D 3
+#define RVFDQ_LS_FS_WIDTH_Q 4
+#define RVFDQ_OPCODE_FL 0x07
+#define RVFDQ_OPCODE_FS 0x27
+
+/* parts of opcode for RVV */
+#define RVV_OPCODE_VECTOR 0x57
+#define RVV_VL_VS_WIDTH_8 0
+#define RVV_VL_VS_WIDTH_16 5
+#define RVV_VL_VS_WIDTH_32 6
+#define RVV_VL_VS_WIDTH_64 7
+#define RVV_OPCODE_VL RVFDQ_OPCODE_FL
+#define RVV_OPCODE_VS RVFDQ_OPCODE_FS
/* parts of opcode for RVC*/
#define RVC_OPCODE_C0 0x0
@@ -304,6 +324,15 @@ static __always_inline bool riscv_insn_is_branch(u32 code)
(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
+#define RVG_EXTRACT_SYSTEM_CSR(x) \
+ ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
+
+#define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
+ ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
+ RVFDQ_FL_FS_WIDTH_MASK); })
+
+#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
+
/*
* Get the immediate from a J-type instruction.
*
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 3bfa223facd0..09f8dbad3dee 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -20,6 +20,7 @@
extern unsigned long riscv_v_vsize;
void riscv_v_setup_vsize(void);
+bool riscv_v_first_use_handler(struct pt_regs *regs);
static __always_inline bool has_vector(void)
{
@@ -163,6 +164,7 @@ static inline void __switch_to_vector(struct task_struct *prev,
struct pt_regs;
static __always_inline bool has_vector(void) { return false; }
+static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; }
static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
#define riscv_v_vsize (0)
#define riscv_v_setup_vsize() do {} while (0)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index f6fda94e8e59..2a98fe74274e 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -24,6 +24,7 @@
#include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/thread_info.h>
+#include <asm/vector.h>
int show_unhandled_signals = 1;
@@ -135,8 +136,17 @@ DO_ERROR_INFO(do_trap_insn_misaligned,
SIGBUS, BUS_ADRALN, "instruction address misaligned");
DO_ERROR_INFO(do_trap_insn_fault,
SIGSEGV, SEGV_ACCERR, "instruction access fault");
-DO_ERROR_INFO(do_trap_insn_illegal,
- SIGILL, ILL_ILLOPC, "illegal instruction");
+
+asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *regs)
+{
+ if (has_vector() && user_mode(regs)) {
+ if (riscv_v_first_use_handler(regs))
+ return;
+ }
+ do_trap_error(regs, SIGILL, ILL_ILLOPC, regs->epc,
+ "Oops - illegal instruction");
+}
+
DO_ERROR_INFO(do_trap_load_fault,
SIGSEGV, SEGV_ACCERR, "load access fault");
#ifndef CONFIG_RISCV_M_MODE
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 082baf2a061f..f13d2f3d77fb 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -4,9 +4,19 @@
* Author: Andy Chiu <andy.chiu@sifive.com>
*/
#include <linux/export.h>
+#include <linux/sched/signal.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <asm/thread_info.h>
+#include <asm/processor.h>
+#include <asm/insn.h>
#include <asm/vector.h>
#include <asm/csr.h>
+#include <asm/ptrace.h>
+#include <asm/bug.h>
unsigned long riscv_v_vsize __read_mostly;
EXPORT_SYMBOL_GPL(riscv_v_vsize);
@@ -19,3 +29,83 @@ void riscv_v_setup_vsize(void)
riscv_v_disable();
}
+static bool insn_is_vector(u32 insn_buf)
+{
+ u32 opcode = insn_buf & __INSN_OPCODE_MASK;
+ bool is_vector = false;
+ u32 width, csr;
+
+ /*
+ * All V-related instructions, including CSR operations are 4-Byte. So,
+ * do not handle if the instruction length is not 4-Byte.
+ */
+ if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
+ return false;
+
+ switch (opcode) {
+ case RVV_OPCODE_VECTOR:
+ is_vector = true;
+ break;
+ case RVV_OPCODE_VL:
+ case RVV_OPCODE_VS:
+ width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
+ if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
+ width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
+ is_vector = true;
+ break;
+ case RVG_OPCODE_SYSTEM:
+ csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
+ if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
+ (csr >= CSR_VL && csr <= CSR_VLENB))
+ is_vector = true;
+ break;
+ }
+ return is_vector;
+}
+
+static int riscv_v_thread_zalloc(void)
+{
+ void *datap;
+
+ datap = kzalloc(riscv_v_vsize, GFP_KERNEL);
+ if (!datap)
+ return -ENOMEM;
+ current->thread.vstate.datap = datap;
+ memset(¤t->thread.vstate, 0, offsetof(struct __riscv_v_ext_state,
+ datap));
+ return 0;
+}
+
+bool riscv_v_first_use_handler(struct pt_regs *regs)
+{
+ __user u32 *epc = (u32 *)regs->epc;
+ u32 insn = (u32)regs->badaddr;
+
+ /* If V has been enabled then it is not the first-use trap */
+ if (riscv_v_vstate_query(regs))
+ return false;
+
+ /* Get the instruction */
+ if (!insn) {
+ if (__get_user(insn, epc))
+ return false;
+ }
+ /* Filter out non-V instructions */
+ if (!insn_is_vector(insn))
+ return false;
+
+ /* Sanity check. datap should be null by the time of the first-use trap */
+ WARN_ON(current->thread.vstate.datap);
+ /*
+ * Now we sure that this is a V instruction. And it executes in the
+ * context where VS has been off. So, try to allocate the user's V
+ * context and resume execution.
+ */
+ if (riscv_v_thread_zalloc()) {
+ force_sig(SIGKILL);
+ return true;
+ }
+ riscv_v_vstate_on(regs);
+ return true;
+}
+
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-03-17 11:37 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-17 11:35 [PATCH -next v15 00/19] riscv: Add vector ISA support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 01/19] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Andy Chiu
2023-03-20 13:02 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-20 13:05 ` Conor Dooley
2023-03-20 14:46 ` Andy Chiu
2023-03-20 14:54 ` Conor Dooley
2023-03-22 1:54 ` Guo Ren
2023-03-23 10:21 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-20 13:07 ` Conor Dooley
2023-03-23 10:23 ` Björn Töpel
2023-03-17 11:35 ` Andy Chiu [this message]
2023-03-20 13:27 ` [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap Conor Dooley
2023-03-23 10:29 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-20 13:36 ` Conor Dooley
2023-03-23 7:50 ` Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-23 10:36 ` Björn Töpel
2023-03-23 14:39 ` Guo Ren
2023-03-17 11:35 ` [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-20 13:40 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-17 11:54 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-17 12:02 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-03-17 15:46 ` Nathan Chancellor
2023-03-20 13:47 ` Conor Dooley
2023-03-23 10:44 ` [PATCH -next v15 00/19] riscv: Add vector ISA support Björn Töpel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230317113538.10878-11-andy.chiu@sifive.com \
--to=andy.chiu@sifive.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@atishpatra.org \
--cc=bjorn@rivosinc.com \
--cc=conor.dooley@microchip.com \
--cc=greentime.hu@sifive.com \
--cc=guoren@kernel.org \
--cc=guoren@linux.alibaba.com \
--cc=heiko.stuebner@vrull.eu \
--cc=jszhang@kernel.org \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=liaochang1@huawei.com \
--cc=linux-riscv@lists.infradead.org \
--cc=mnissler@rivosinc.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=richard.henderson@linaro.org \
--cc=vincent.chen@sifive.com \
--cc=vineetg@rivosinc.com \
--cc=xianting.tian@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).