From: Andy Chiu <andy.chiu@sifive.com>
To: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
anup@brainfault.org, atishp@atishpatra.org,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org
Cc: vineetg@rivosinc.com, greentime.hu@sifive.com,
guoren@linux.alibaba.com, Vincent Chen <vincent.chen@sifive.com>,
Andy Chiu <andy.chiu@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Li Zhengyu <lizhengyu3@huawei.com>,
Xianting Tian <xianting.tian@linux.alibaba.com>,
Liao Chang <liaochang1@huawei.com>,
Masahiro Yamada <masahiroy@kernel.org>,
Conor Dooley <conor.dooley@microchip.com>,
Andrew Jones <ajones@ventanamicro.com>,
Jisheng Zhang <jszhang@kernel.org>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context
Date: Fri, 17 Mar 2023 11:35:26 +0000 [thread overview]
Message-ID: <20230317113538.10878-8-andy.chiu@sifive.com> (raw)
In-Reply-To: <20230317113538.10878-1-andy.chiu@sifive.com>
From: Greentime Hu <greentime.hu@sifive.com>
This patch is used to detect the size of CPU vector registers and use
riscv_v_vsize to save the size of all the vector registers. It assumes all
harts has the same capabilities in a SMP system.
Co-developed-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Co-developed-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/vector.h | 5 +++++
arch/riscv/kernel/Makefile | 1 +
arch/riscv/kernel/cpufeature.c | 2 ++
arch/riscv/kernel/vector.c | 21 +++++++++++++++++++++
4 files changed, 29 insertions(+)
create mode 100644 arch/riscv/kernel/vector.c
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index dfe5a321b2b4..18448e24d77b 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -13,6 +13,9 @@
#include <asm/hwcap.h>
#include <asm/csr.h>
+extern unsigned long riscv_v_vsize;
+void riscv_v_setup_vsize(void);
+
static __always_inline bool has_vector(void)
{
return riscv_has_extension_likely(RISCV_ISA_EXT_v);
@@ -31,6 +34,8 @@ static __always_inline void riscv_v_disable(void)
#else /* ! CONFIG_RISCV_ISA_V */
static __always_inline bool has_vector(void) { return false; }
+#define riscv_v_vsize (0)
+#define riscv_v_setup_vsize() do {} while (0)
#endif /* CONFIG_RISCV_ISA_V */
diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
index 4cf303a779ab..48d345a5f326 100644
--- a/arch/riscv/kernel/Makefile
+++ b/arch/riscv/kernel/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_MMU) += vdso.o vdso/
obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o
obj-$(CONFIG_FPU) += fpu.o
+obj-$(CONFIG_RISCV_ISA_V) += vector.o
obj-$(CONFIG_SMP) += smpboot.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP) += cpu_ops.o
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index bb1d14e08a0a..265070f0158f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -22,6 +22,7 @@
#include <asm/processor.h>
#include <asm/smp.h>
#include <asm/switch_to.h>
+#include <asm/vector.h>
#define NUM_ALPHA_EXTS ('z' - 'a' + 1)
@@ -258,6 +259,7 @@ void __init riscv_fill_hwcap(void)
}
if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+ riscv_v_setup_vsize();
/*
* ISA string in device tree might have 'v' flag, but
* CONFIG_RISCV_ISA_V is disabled in kernel.
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
new file mode 100644
index 000000000000..082baf2a061f
--- /dev/null
+++ b/arch/riscv/kernel/vector.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2023 SiFive
+ * Author: Andy Chiu <andy.chiu@sifive.com>
+ */
+#include <linux/export.h>
+
+#include <asm/vector.h>
+#include <asm/csr.h>
+
+unsigned long riscv_v_vsize __read_mostly;
+EXPORT_SYMBOL_GPL(riscv_v_vsize);
+
+void riscv_v_setup_vsize(void)
+{
+ /* There are 32 vector registers with vlenb length. */
+ riscv_v_enable();
+ riscv_v_vsize = csr_read(CSR_VLENB) * 32;
+ riscv_v_disable();
+}
+
--
2.17.1
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next prev parent reply other threads:[~2023-03-17 11:37 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-17 11:35 [PATCH -next v15 00/19] riscv: Add vector ISA support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 01/19] riscv: Rename __switch_to_aux() -> fpu Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 02/19] riscv: Extending cpufeature.c to detect V-extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 03/19] riscv: Add new csr defines related to vector extension Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 04/19] riscv: Clear vector regfile on bootup Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 05/19] riscv: Disable Vector Instructions for kernel itself Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 06/19] riscv: Introduce Vector enable/disable helpers Andy Chiu
2023-03-17 11:35 ` Andy Chiu [this message]
2023-03-20 13:02 ` [PATCH -next v15 07/19] riscv: Introduce riscv_v_vsize to record size of Vector context Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 08/19] riscv: Introduce struct/helpers to save/restore per-task Vector state Andy Chiu
2023-03-20 13:05 ` Conor Dooley
2023-03-20 14:46 ` Andy Chiu
2023-03-20 14:54 ` Conor Dooley
2023-03-22 1:54 ` Guo Ren
2023-03-23 10:21 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 09/19] riscv: Add task switch support for vector Andy Chiu
2023-03-20 13:07 ` Conor Dooley
2023-03-23 10:23 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 10/19] riscv: Allocate user's vector context in the first-use trap Andy Chiu
2023-03-20 13:27 ` Conor Dooley
2023-03-23 10:29 ` Björn Töpel
2023-03-17 11:35 ` [PATCH -next v15 11/19] riscv: Add ptrace vector support Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 12/19] riscv: signal: check fp-reserved words unconditionally Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 13/19] riscv: signal: Add sigcontext save/restore for vector Andy Chiu
2023-03-20 13:36 ` Conor Dooley
2023-03-23 7:50 ` Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 14/19] riscv: signal: Report signal frame size to userspace via auxv Andy Chiu
2023-03-23 10:36 ` Björn Töpel
2023-03-23 14:39 ` Guo Ren
2023-03-17 11:35 ` [PATCH -next v15 15/19] riscv: signal: validate altstack to reflect Vector Andy Chiu
2023-03-20 13:40 ` Conor Dooley
2023-03-17 11:35 ` [PATCH -next v15 16/19] riscv: prevent stack corruption by reserving task_pt_regs(p) early Andy Chiu
2023-03-17 11:35 ` [PATCH -next v15 17/19] riscv: kvm: Add V extension to KVM ISA Andy Chiu
2023-03-17 11:54 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 18/19] riscv: KVM: Add vector lazy save/restore support Andy Chiu
2023-03-17 12:02 ` Anup Patel
2023-03-17 11:35 ` [PATCH -next v15 19/19] riscv: Enable Vector code to be built Andy Chiu
2023-03-17 15:46 ` Nathan Chancellor
2023-03-20 13:47 ` Conor Dooley
2023-03-23 10:44 ` [PATCH -next v15 00/19] riscv: Add vector ISA support Björn Töpel
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