From: Drew Fustini <dfustini@baylibre.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Adrien Ricciardi" <aricciardi@baylibre.com>,
"Nicolas Pitre" <npitre@baylibre.com>,
"Fenghua Yu" <fenghua.yu@intel.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Babu Moger" <babu.moger@amd.com>,
"Peter Newman" <peternewman@google.com>,
x86@kernel.org, "Rob Herring" <robh+dt@kernel.org>,
"James Morse" <james.morse@arm.com>
Cc: Drew Fustini <dfustini@baylibre.com>
Subject: [RFC PATCH 01/21] RISC-V: Detect the Ssqosid extension
Date: Wed, 19 Apr 2023 04:10:51 -0700 [thread overview]
Message-ID: <20230419111111.477118-2-dfustini@baylibre.com> (raw)
In-Reply-To: <20230419111111.477118-1-dfustini@baylibre.com>
Ssqosid is the Supervisor QoS ID extension defined in the RISC-V CBQRI
(Capacity and Bandwidth QoS Register Interface) specification.
Link: https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
Signed-off-by: Kornel Dulęba <mindal@semihalf.com>
[dfustini: rebase from v6.0 to v6.3]
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
---
Note:
- A version of this patch rebased on riscv/for-next was already
submitted as an RFC to linux-riscv [1] with Message-ID:
20230410043646.3138446-1-dfustini@baylibre.com
- This patch is included in this RFC series so as to provide a cohesive
demonstration in one series.
[1] https://lore.kernel.org/lkml/20230410043646.3138446-1-dfustini@baylibre.com/
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
3 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index e3021b2590de..255c5c4d0a24 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -42,6 +42,8 @@
#define RISCV_ISA_EXT_ZBB 30
#define RISCV_ISA_EXT_ZICBOM 31
#define RISCV_ISA_EXT_ZIHINTPAUSE 32
+#define RISCV_ISA_EXT_SSQOSID 35
+
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 8400f0cc9704..d1441872f173 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -189,6 +189,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
+ __RISCV_ISA_EXT_DATA(ssqosid, RISCV_ISA_EXT_SSQOSID),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 59d58ee0f68d..80317d2d3975 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -222,6 +222,7 @@ void __init riscv_fill_hwcap(void)
} else {
/* sorted alphabetically */
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
+ SET_ISA_EXT_MAP("ssqosid", RISCV_ISA_EXT_SSQOSID);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
--
2.34.1
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next prev parent reply other threads:[~2023-04-19 11:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 11:10 [RFC PATCH 00/21] RISC-V: QoS: add CBQRI resctrl interface Drew Fustini
2023-04-19 11:10 ` Drew Fustini [this message]
2023-04-19 11:10 ` [RFC PATCH 02/21] RISC-V: Add support for sqoscfg CSR Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 03/21] RISC-V: QoS: define properties of CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 04/21] RISC-V: QoS: define CBQRI capacity and bandwidth capabilities Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 05/21] RISC-V: QoS: define prototypes for resctrl interface Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 06/21] RISC-V: QoS: define CBQRI resctrl resources and domains Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 07/21] RISC-V: QoS: add resctrl interface for CBQRI controllers Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 08/21] RISC-V: QoS: expose implementation to resctrl Drew Fustini
2023-04-19 11:10 ` [RFC PATCH 09/21] RISC-V: QoS: add late_initcall to setup resctrl interface Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 10/21] RISC-V: QoS: make CONFIG_RISCV_ISA_SSQOSID select resctrl Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 11/21] RISC-V: QoS: add to build when CONFIG_RISCV_ISA_SSQOSID set Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 12/21] dt-bindings: riscv: add riscv,cbqri bindings Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 13/21] DO_NOT_MERGE dt-bindings: add foobar vendor-prefix Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 14/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC cache controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 15/21] DO_NOT_MERGE dt-bindings: soc: add Foobar SoC memory controller Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 16/21] DO_NOT_MERGE soc: add Foobar SoC cache controller driver Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 17/21] DO_NOT_MERGE soc: add Foobar SoC memory " Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 18/21] DO_NOT_MERGE soc: build Foobar SoC drivers Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 19/21] DO_NOT_MERGE riscv: dts: qemu: add dump from riscv-cbqri-rfc Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 20/21] DO_NOT_MERGE riscv: dts: qemu: add cbqri-capable controllers Drew Fustini
2023-04-19 11:11 ` [RFC PATCH 21/21] DO_NOT_MERGE riscv: dts: build qemu virt device tree Drew Fustini
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