From: Qingfang Deng <dqfext@gmail.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Andrew Jones <ajones@ventanamicro.com>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908
Date: Mon, 11 Mar 2024 14:30:18 +0800 [thread overview]
Message-ID: <20240311063018.1886757-1-dqfext@gmail.com> (raw)
T-Head C908 has the same IRQ num and CSR as previous C9xx cores, but
reports non-zero marchid and mimpid. Remove the ID checks.
Fixes: 65e9fb081877 ("drivers/perf: riscv_pmu_sbi: add support for PMU variant on T-Head C9xx cores")
Signed-off-by: Qingfang Deng <dqfext@gmail.com>
---
arch/riscv/errata/thead/errata.c | 4 ----
drivers/perf/riscv_pmu_sbi.c | 4 +---
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index b1c410bbc1ae..49ccad5b21bb 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -125,10 +125,6 @@ static bool errata_probe_pmu(unsigned int stage,
if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PMU))
return false;
- /* target-c9xx cores report arch_id and impid as 0 */
- if (arch_id != 0 || impid != 0)
- return false;
-
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
return false;
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 452aab49db1e..87b83184383a 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -811,9 +811,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde
riscv_pmu_irq_num = RV_IRQ_PMU;
riscv_pmu_use_irq = true;
} else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) &&
- riscv_cached_mvendorid(0) == THEAD_VENDOR_ID &&
- riscv_cached_marchid(0) == 0 &&
- riscv_cached_mimpid(0) == 0) {
+ riscv_cached_mvendorid(0) == THEAD_VENDOR_ID) {
riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU;
riscv_pmu_use_irq = true;
}
--
2.34.1
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next reply other threads:[~2024-03-11 6:31 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-11 6:30 Qingfang Deng [this message]
2024-03-11 7:13 ` [PATCH] perf: RISC-V: fix IRQ detection on T-Head C908 Inochi Amaoto
2024-03-11 7:56 ` Qingfang Deng
2024-03-12 14:07 ` Conor Dooley
2024-03-13 1:31 ` Inochi Amaoto
2024-03-14 20:41 ` Conor Dooley
2024-03-15 5:23 ` Inochi Amaoto
2024-04-12 6:27 ` Yangyu Chen
2024-04-12 7:40 ` Conor Dooley
2024-03-15 8:11 ` Andrew Jones
2024-03-15 12:22 ` Inochi Amaoto
2024-03-18 22:46 ` Atish Patra
2024-03-18 23:48 ` Conor Dooley
2024-03-19 0:48 ` Atish Patra
2024-03-19 9:06 ` Conor Dooley
2024-03-19 13:39 ` Andrew Jones
2024-03-19 15:36 ` Conor Dooley
2024-03-19 20:11 ` Atish Patra
2024-03-19 20:08 ` Atish Patra
2024-04-12 6:09 ` Yangyu Chen
2024-04-17 6:29 ` Guo Ren
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