From: Conor Dooley <conor@kernel.org>
To: Samuel Ortiz <sameo@rivosinc.com>
Cc: "Hongren (Zenithal) Zheng" <i@zenithal.me>,
Palmer Dabbelt <palmer@rivosinc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <anup@brainfault.org>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-api@vger.kernel.org,
Michael Kerrisk <mtk.manpages@gmail.com>,
linux-man@vger.kernel.org, Jiatai He <jiatai2021@iscas.ac.cn>,
Heiko Stuebner <heiko@sntech.de>
Subject: Re: [PATCH v3 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto
Date: Thu, 24 Nov 2022 17:54:00 +0000 [thread overview]
Message-ID: <27d0de3e-1006-dd3a-0e91-ae8025ef8426@kernel.org> (raw)
In-Reply-To: <Y3+rE6j/CzTpINi+@vermeer>
On 24/11/2022 17:34, Samuel Ortiz wrote:
> On Thu, Nov 24, 2022 at 05:20:37PM +0000, Conor Dooley wrote:
>> On 24/11/2022 17:12, Samuel Ortiz wrote:
>>> [You don't often get email from sameo@rivosinc.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>>>
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Thu, Nov 24, 2022 at 11:55:01AM +0000, Conor Dooley wrote:
>>>> On Thu, Nov 24, 2022 at 11:47:30AM +0100, Samuel Ortiz wrote:
>>>>
>>>>> Patch #1 is definitely needed regardless of which interface we pick for
>>>>> exposing the ISA strings to userspace.
>>>>
>>>> I took another look at #1, and I feel more confused about what
>>>> constitutes canonical order than I did before! If you know better than
>>>> I, and you probably do since you're interested in these 6 month old
>>>> patches, some insight would be appreciated!
>>>
>>> Assuming we don't go with hwcap, I dont think the order of the
>>> riscv_isa_ext_id enum matters that much?
>>
>> The chief put it in canonical order so that's good enough for me!
>>
>>>
>>> iiuc we're building the cpuinfo string from the riscv_isa_ext_data
>>> array, and I think the current code is incorrect:
>>>
>>> static struct riscv_isa_ext_data isa_ext_arr[] = {
>>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
>>> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
>>> __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),
>>> __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
>>> __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>>> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>>> __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
>>> };
>>>
>>> zicbom and zihintpause should come before supervisor level extensions.
>>> I'm going to send a patch for that.
>>
>> idk, Palmer explicitly re-ordered this:
>> https://lore.kernel.org/linux-riscv/20220920204518.10988-1-palmer@rivosinc.com/
>>
>> By my reading of the isa manual, what Palmer did is correct as
>> those are not "Additional Standard Extensions". /shrug
>
> Hmm, by their name (Z[a-b]+) they are Additional Standard Extensions.
> What am I missing?
Right, and this is where I get confused. Zam and Ztso *are* Additional
Standard Extensions, I think we can agree on that one? For those
extensions:
\chapter{``Ztso'' Standard Extension for Total Store Ordering, v0.1}
\chapter{``Zam'' Standard Extension for Misaligned Atomics, v0.1}
They're also called out specifically in the table:
https://github.com/riscv/riscv-isa-manual/blob/master/src/naming.tex#L147
For Zihintpause however:
\chapter{``Zihintpause'' Pause Hint, Version 2.0}
See what I mean? I looked at the specs for the bitmanip stuff and for
crypto, which both never mention being standard.
That table has the caption:
> The table also defines the canonical order in which extension names
> must appear in the name string, with top-to-bottom in table
> indicating first-to-last in the name string.
It only calls out Zicsr, Zifencei, Zam and Ztso are being permitted
before Sdef, but as I said I am not a specs person, so perhaps some
of the extensions in question are intended to go there but have not
yet been merged into the isa manual doc. Zihintpause *is* in the
isa manual though but not specifically called out.
Anyways, hopefully that at least helps with my line of thinking!
Conor.
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next prev parent reply other threads:[~2022-11-24 17:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-12 18:44 [PATCH v3 0/3] RISC-V: Add Bitmanip/Scalar Crypto HWCAP Hongren (Zenithal) Zheng
2022-06-12 18:46 ` [PATCH v3 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Hongren (Zenithal) Zheng
2022-11-24 9:19 ` Samuel Ortiz
2022-11-24 11:53 ` Conor Dooley
2022-06-12 18:46 ` [PATCH v3 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto Hongren (Zenithal) Zheng
2022-11-24 9:30 ` Samuel Ortiz
2022-11-24 9:58 ` Conor Dooley
2022-11-24 10:47 ` Samuel Ortiz
2022-11-24 11:55 ` Conor Dooley
2022-11-24 17:12 ` Samuel Ortiz
2022-11-24 17:20 ` Conor Dooley
2022-11-24 17:34 ` Samuel Ortiz
2022-11-24 17:54 ` Conor Dooley [this message]
2022-11-24 18:09 ` Samuel Ortiz
2022-06-12 18:47 ` [PATCH v3 3/3] RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT Hongren (Zenithal) Zheng
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