From: Vineet Gupta <vineetg@rivosinc.com>
To: Chris Stillson <stillson@rivosinc.com>
Cc: Greentime Hu <greentime.hu@sifive.com>,
Guo Ren <guoren@linux.alibaba.com>,
Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <keescook@chromium.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Oleg Nesterov <oleg@redhat.com>, Guo Ren <guoren@kernel.org>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Arnd Bergmann <arnd@arndb.de>, Heiko Stuebner <heiko@sntech.de>,
Jisheng Zhang <jszhang@kernel.org>, Dao Lu <daolu@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Andy Chiu <andy.chiu@sifive.com>, Guo Ren <guoren@kernel.org>,
lkml <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-mm@kvack.org
Subject: Re: [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features.
Date: Thu, 3 Nov 2022 21:33:39 -0700 [thread overview]
Message-ID: <3d8aa022-a73e-aa27-5219-12dcf9f20443@rivosinc.com> (raw)
In-Reply-To: <20220921214439.1491510-5-stillson@rivosinc.com>
On 9/21/22 14:43, Chris Stillson wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
>
> This patch is used to detect vector support status of CPU and use
> riscv_vsize to save the size of all the vector registers. It assumes
> all harts has the same capabilities in SMP system.
Patch title is horrible. The meat of patch is vector state save/restore,
but no users of it yet. And then there are random unrelated snippets
thrown in same patch.
> +#ifdef CONFIG_FPU
> +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu);
> +#endif
This needs to be broken out to a FPU patch which actually uses
cpu_hwcap_fpu.
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector);
> +unsigned long riscv_vsize __read_mostly;
> +#endif
I'd move this patch v2/17 as part of detection etc.
> +#ifdef CONFIG_VECTOR
> + if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
> + static_branch_enable(&cpu_hwcap_vector);
Ditto.
> + /* There are 32 vector registers with vlenb length. */
> + rvv_enable();
> + riscv_vsize = csr_read(CSR_VLENB) * 32;
Ditto.
> + rvv_disable();
But guess these needs to be added first as well, see below.
> +#ifdef CONFIG_VECTOR
> +#include <asm/vector.h>
> +EXPORT_SYMBOL(rvv_enable);
> +EXPORT_SYMBOL(rvv_disable);
As suggested in prior review comment, we don't need to EXPORT these, for
now at least.
> diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S
> new file mode 100644
> index 000000000000..9f7dc70c4443
> --- /dev/null
> +++ b/arch/riscv/kernel/vector.S
> @@ -0,0 +1,93 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2012 Regents of the University of California
> + * Copyright (C) 2017 SiFive
> + * Copyright (C) 2019 Alibaba Group Holding Limited
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation, version 2.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
SPDX hdr ...
> +
> +#include <linux/linkage.h>
> +
> +#include <asm/asm.h>
> +#include <asm/csr.h>
> +#include <asm/asm-offsets.h>
> +
> +#define vstatep a0
> +#define datap a1
> +#define x_vstart t0
> +#define x_vtype t1
> +#define x_vl t2
> +#define x_vcsr t3
> +#define incr t4
> +#define status t5
> +
A few words here as to when is this save/restore done.
Perhaps best to add this code in the patch which actually uses these.
> +ENTRY(__vstate_save)
> + li status, SR_VS
> + csrs CSR_STATUS, status
> +
> + csrr x_vstart, CSR_VSTART
> + csrr x_vtype, CSR_VTYPE
> + csrr x_vl, CSR_VL
> + csrr x_vcsr, CSR_VCSR
> + vsetvli incr, x0, e8, m8, ta, ma
> + vse8.v v0, (datap)
> + add datap, datap, incr
> + vse8.v v8, (datap)
> + add datap, datap, incr
> + vse8.v v16, (datap)
> + add datap, datap, incr
> + vse8.v v24, (datap)
> +
> + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep)
> + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep)
> + REG_S x_vl, RISCV_V_STATE_VL(vstatep)
> + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> +
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(__vstate_save)
> +
> +ENTRY(__vstate_restore)
> + li status, SR_VS
> + csrs CSR_STATUS, status
This is rvv_enable code duplicated inline.
> +
> + vsetvli incr, x0, e8, m8, ta, ma
> + vle8.v v0, (datap)
> + add datap, datap, incr
> + vle8.v v8, (datap)
> + add datap, datap, incr
> + vle8.v v16, (datap)
> + add datap, datap, incr
> + vle8.v v24, (datap)
> +
> + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep)
> + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep)
> + REG_L x_vl, RISCV_V_STATE_VL(vstatep)
> + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep)
> + vsetvl x0, x_vl, x_vtype
> + csrw CSR_VSTART, x_vstart
> + csrw CSR_VCSR, x_vcsr
> +
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(__vstate_restore)
> +
> +ENTRY(rvv_enable)
> + li status, SR_VS
> + csrs CSR_STATUS, status
> + ret
> +ENDPROC(rvv_enable)
> +
> +ENTRY(rvv_disable)
> + li status, SR_VS
> + csrc CSR_STATUS, status
> + ret
> +ENDPROC(rvv_disable)
I'd suggest these be made asm macros, to avoid function call overhead
and duplication as in save/restore above.
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next prev parent reply other threads:[~2022-11-04 4:34 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 21:43 [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
2022-09-21 21:43 ` [PATCH v12 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
[not found] ` <4b6e20fb-d013-0a09-0b74-b6c46e045af3@rivosinc.com>
[not found] ` <CAJF2gTSPoKu_owEb6+MLhAgK5nz2FTRDkTn4qfXF4KyA-XTwvw@mail.gmail.com>
[not found] ` <CAJF2gTT_z96V3kjPtr9hpTq8XRn0x=91wFNPYFFdetAA2u-01Q@mail.gmail.com>
2022-11-04 9:13 ` Conor.Dooley
2022-11-04 18:04 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2023-01-23 11:24 ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 04/17] riscv: Add vector feature to compile Chris Stillson
2022-11-07 17:21 ` Björn Töpel
2022-11-08 0:04 ` Vineet Gupta
2022-11-08 7:56 ` Conor Dooley
2022-11-08 17:17 ` Vineet Gupta
2022-11-08 17:22 ` Conor Dooley
2022-11-13 16:16 ` Conor.Dooley
2022-11-15 17:38 ` Vineet Gupta
2022-11-15 22:17 ` Conor Dooley
2022-12-15 0:40 ` Atish Patra
2022-09-21 21:43 ` [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-22 4:23 ` Samuel Holland
2022-09-23 16:27 ` Chris Stillson
2022-09-24 18:01 ` Conor Dooley
2022-11-04 4:10 ` Vineet Gupta
2022-11-04 4:33 ` Vineet Gupta [this message]
2022-09-21 21:43 ` [PATCH v12 06/17] riscv: Reset vector register Chris Stillson
2022-11-04 5:01 ` Vineet Gupta
2022-11-04 8:45 ` Guo Ren
2023-01-20 12:20 ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-11-04 5:13 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 08/17] riscv: Add task switch support for vector Chris Stillson
2022-11-04 22:08 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 09/17] riscv: Add ptrace vector support Chris Stillson
2022-11-08 1:38 ` Vineet Gupta
2022-11-14 20:01 ` Arnd Bergmann
2022-09-21 21:43 ` [PATCH v12 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-11-09 1:27 ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 21:43 ` [PATCH v12 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 21:43 ` [PATCH v12 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 21:43 ` [PATCH v12 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 21:43 ` [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 21:43 ` [PATCH v12 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 21:43 ` [PATCH v12 17/17] riscv: prctl to enable vector commands Chris Stillson
2022-12-09 5:16 ` RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Vineet Gupta
2022-12-09 6:27 ` Palmer Dabbelt
2022-12-09 7:42 ` Andrew Waterman
2022-12-09 10:02 ` Florian Weimer
2022-12-09 12:21 ` Darius Rad
2022-12-09 12:32 ` Florian Weimer
2022-12-09 12:42 ` Darius Rad
2022-12-09 13:04 ` Florian Weimer
2022-12-09 17:21 ` Palmer Dabbelt
2022-12-09 19:42 ` Vineet Gupta
2022-12-09 19:58 ` Andrew Waterman
2022-12-13 16:43 ` Darius Rad
2022-12-14 20:07 ` Vineet Gupta
2022-12-14 23:13 ` Samuel Holland
2022-12-15 2:09 ` Darius Rad
2022-12-15 11:48 ` Björn Töpel
2022-12-15 12:28 ` Florian Weimer
2022-12-15 15:33 ` Richard Henderson
2022-12-15 18:57 ` Vineet Gupta
2022-12-15 18:59 ` Andrew Pinski
2022-12-15 19:01 ` Andrew Pinski
2022-12-15 19:56 ` Richard Henderson
2022-12-09 13:58 ` Icenowy Zheng
2023-01-23 11:20 ` [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Heiko Stübner
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