Re: [PATCH v12 04/17] riscv: Add vector feature to compile

[<Conor.Dooley@microchip.com>]

On 07/11/2022 17:21, Björn Töpel wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> [Cropping the huge Cc:-list.]
> 
> Chris Stillson <stillson@rivosinc.com> writes:
> 
>> From: Guo Ren <guoren@linux.alibaba.com>
>>
>> This patch adds a new config option which could enable assembler's
>> vector feature.
>>
>> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
>> Co-developed-by: Greentime Hu <greentime.hu@sifive.com>
>> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
>> ---
>>  arch/riscv/Kconfig  | 15 +++++++++++++--
>>  arch/riscv/Makefile |  1 +
>>  2 files changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index ed66c31e4655..e294d85bfb7d 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -432,7 +432,17 @@ config FPU
>>
>>         If you don't know what to do here, say Y.
>>
>> -endmenu # "Platform type"
>> +config VECTOR
>> +     bool "VECTOR support"
>> +     depends on GCC_VERSION >= 120000 || CLANG_VERSION >= 130000
>> +     default n
>> +     help
>> +       Say N here if you want to disable all vector related procedure
>> +       in the kernel.
>> +
>> +       If you don't know what to do here, say Y.
>> +
>> +endmenu
> 
> "VECTOR" is not really consistent to how the other configs are named;
> RISCV_ISA_V, RISCV_ISA_VECTOR, RISCV_VECTOR?

It'd be RISCV_ISA_V to match the others single letter extentions, right?

The toolchain dependency check here also seems rather naive.

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