[PATCH v3 0/2] riscv: KVM: Expose Zicbom to the guest

[PATCH v3 0/2] riscv: KVM: Expose Zicbom to the guest

[Andrew Jones]

Add support for exposing the Zicbom extension to guests. This has been
tested over a QEMU including the Zicbom support [1] ([1] was rebased and
the Zicboz support from it was dropped.) QEMU was further modified to
ensure the cache block size was provided in the DT. kvmtool was also
modified [2] to test the new KVM API and provide the guest the cache
block size in its DT (The kvmtool patches are based on Anup's Svpbmt/Sstc
series [3]). These KVM patches are based on the riscv_init_cbom_blocksize()
cleanup patch from Palmer and the move and expose riscv_cbom_block_size
patch from Anup which was reposted [4]. This series is also available here
[5].

[1] https://gitlab.com/jones-drew/qemu/-/commits/riscv/zicbom
[2] https://github.com/jones-drew/kvmtool/commits/riscv/zicbom
[3] https://github.com/avpatel/kvmtool/commits/riscv_svpbmt_sstc_v1
[4] https://lore.kernel.org/linux-riscv/20220906074509.928865-1-ajones@ventanamicro.com/T/#u
[5] https://github.com/jones-drew/linux/commits/riscv/kvm/zicbom-v3

Thanks,
drew

v3:
 - Added check to ensure the extension is enabled for
   config.get(blocksz) [Atish and Anup]
 - Opportunistically switched all extension checks in
   kvm_riscv_vcpu_update_config() to riscv_isa_extension_available()
   from its __ counterpart
 - Picked up some r-b's

v2:
 - Dropped a patch that output the cache block size to dmesg

Andrew Jones (2):
  RISC-V: KVM: Provide UAPI for Zicbom block size
  RISC-V: KVM: Expose Zicbom to the guest

 arch/riscv/include/uapi/asm/kvm.h |  2 ++
 arch/riscv/kvm/vcpu.c             | 17 +++++++++++++++--
 arch/riscv/mm/cacheflush.c        |  1 +
 3 files changed, 18 insertions(+), 2 deletions(-)

-- 
2.37.2


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[PATCH v3 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size

[Andrew Jones]

We're about to allow guests to use the Zicbom extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 8 ++++++++
 arch/riscv/mm/cacheflush.c        | 1 +
 3 files changed, 10 insertions(+)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index 7351417afd62..b9a4cf36be4b 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -48,6 +48,7 @@ struct kvm_sregs {
 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
 struct kvm_riscv_config {
 	unsigned long isa;
+	unsigned long zicbom_block_size;
 };
 
 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index d0f08d5b4282..2ef33d5d94d1 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -18,6 +18,7 @@
 #include <linux/fs.h>
 #include <linux/kvm_host.h>
 #include <asm/csr.h>
+#include <asm/cacheflush.h>
 #include <asm/hwcap.h>
 
 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
@@ -254,6 +255,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
 	case KVM_REG_RISCV_CONFIG_REG(isa):
 		reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
 		break;
+	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
+		if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
+			return -EINVAL;
+		reg_val = riscv_cbom_block_size;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -311,6 +317,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
 			return -EOPNOTSUPP;
 		}
 		break;
+	case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
+		return -EOPNOTSUPP;
 	default:
 		return -EINVAL;
 	}
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index e5b087be1577..f318b2553612 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -90,6 +90,7 @@ void flush_icache_pte(pte_t pte)
 #endif /* CONFIG_MMU */
 
 unsigned int riscv_cbom_block_size;
+EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
 
 #ifdef CONFIG_RISCV_ISA_ZICBOM
 void riscv_init_cbom_blocksize(void)
-- 
2.37.2


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[PATCH v3 2/2] RISC-V: KVM: Expose Zicbom to the guest

[Andrew Jones]

Guests may use the cbo.inval,clean,flush instructions when the
CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
(for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).

Add Zicbom support for KVM guests which may be enabled and
disabled from KVM userspace using the ISA extension ONE_REG API.

Also opportunistically switch the other isa extension checks in
kvm_riscv_vcpu_update_config() to riscv_isa_extension_available().

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/uapi/asm/kvm.h | 1 +
 arch/riscv/kvm/vcpu.c             | 9 +++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
index b9a4cf36be4b..ed37a4a6e5cf 100644
--- a/arch/riscv/include/uapi/asm/kvm.h
+++ b/arch/riscv/include/uapi/asm/kvm.h
@@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
 	KVM_RISCV_ISA_EXT_M,
 	KVM_RISCV_ISA_EXT_SVPBMT,
 	KVM_RISCV_ISA_EXT_SSTC,
+	KVM_RISCV_ISA_EXT_ZICBOM,
 	KVM_RISCV_ISA_EXT_MAX,
 };
 
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 2ef33d5d94d1..74d1532b26c0 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
 	RISCV_ISA_EXT_m,
 	RISCV_ISA_EXT_SVPBMT,
 	RISCV_ISA_EXT_SSTC,
+	RISCV_ISA_EXT_ZICBOM,
 };
 
 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -792,11 +793,15 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
 {
 	u64 henvcfg = 0;
 
-	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT))
+	if (riscv_isa_extension_available(isa, SVPBMT))
 		henvcfg |= ENVCFG_PBMTE;
 
-	if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC))
+	if (riscv_isa_extension_available(isa, SSTC))
 		henvcfg |= ENVCFG_STCE;
+
+	if (riscv_isa_extension_available(isa, ZICBOM))
+		henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
+
 	csr_write(CSR_HENVCFG, henvcfg);
 #ifdef CONFIG_32BIT
 	csr_write(CSR_HENVCFGH, henvcfg >> 32);
-- 
2.37.2


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Re: [PATCH v3 2/2] RISC-V: KVM: Expose Zicbom to the guest

[Atish Patra]

On Fri, Sep 9, 2022 at 7:44 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> Guests may use the cbo.inval,clean,flush instructions when the
> CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
> (for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).
>
> Add Zicbom support for KVM guests which may be enabled and
> disabled from KVM userspace using the ISA extension ONE_REG API.
>
> Also opportunistically switch the other isa extension checks in
> kvm_riscv_vcpu_update_config() to riscv_isa_extension_available().
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>
> ---
>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>  arch/riscv/kvm/vcpu.c             | 9 +++++++--
>  2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index b9a4cf36be4b..ed37a4a6e5cf 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
>         KVM_RISCV_ISA_EXT_M,
>         KVM_RISCV_ISA_EXT_SVPBMT,
>         KVM_RISCV_ISA_EXT_SSTC,
> +       KVM_RISCV_ISA_EXT_ZICBOM,
>         KVM_RISCV_ISA_EXT_MAX,
>  };
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 2ef33d5d94d1..74d1532b26c0 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
>         RISCV_ISA_EXT_m,
>         RISCV_ISA_EXT_SVPBMT,
>         RISCV_ISA_EXT_SSTC,
> +       RISCV_ISA_EXT_ZICBOM,
>  };
>
>  static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
> @@ -792,11 +793,15 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
>  {
>         u64 henvcfg = 0;
>
> -       if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT))
> +       if (riscv_isa_extension_available(isa, SVPBMT))
>                 henvcfg |= ENVCFG_PBMTE;
>
> -       if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC))
> +       if (riscv_isa_extension_available(isa, SSTC))
>                 henvcfg |= ENVCFG_STCE;
> +

Ideally, these should be in a separate patch.

> +       if (riscv_isa_extension_available(isa, ZICBOM))
> +               henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
> +
>         csr_write(CSR_HENVCFG, henvcfg);
>  #ifdef CONFIG_32BIT
>         csr_write(CSR_HENVCFGH, henvcfg >> 32);
> --
> 2.37.2
>

Otherwise, LGTM.
Reviewed-by: Atish Patra <atishp@rivosinc.com>
-- 
Regards,
Atish

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Re: [PATCH v3 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size

[Atish Patra]

On Fri, Sep 9, 2022 at 7:44 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> We're about to allow guests to use the Zicbom extension. KVM
> userspace needs to know the cache block size in order to
> properly advertise it to the guest. Provide a virtual config
> register for userspace to get it with the GET_ONE_REG API, but
> setting it cannot be supported, so disallow SET_ONE_REG.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>  arch/riscv/kvm/vcpu.c             | 8 ++++++++
>  arch/riscv/mm/cacheflush.c        | 1 +
>  3 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 7351417afd62..b9a4cf36be4b 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -48,6 +48,7 @@ struct kvm_sregs {
>  /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
>  struct kvm_riscv_config {
>         unsigned long isa;
> +       unsigned long zicbom_block_size;
>  };
>
>  /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index d0f08d5b4282..2ef33d5d94d1 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -18,6 +18,7 @@
>  #include <linux/fs.h>
>  #include <linux/kvm_host.h>
>  #include <asm/csr.h>
> +#include <asm/cacheflush.h>
>  #include <asm/hwcap.h>
>
>  const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
> @@ -254,6 +255,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
>         case KVM_REG_RISCV_CONFIG_REG(isa):
>                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> +               if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
> +                       return -EINVAL;
> +               reg_val = riscv_cbom_block_size;
> +               break;
>         default:
>                 return -EINVAL;
>         }
> @@ -311,6 +317,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
>                         return -EOPNOTSUPP;
>                 }
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> +               return -EOPNOTSUPP;
>         default:
>                 return -EINVAL;
>         }
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index e5b087be1577..f318b2553612 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -90,6 +90,7 @@ void flush_icache_pte(pte_t pte)
>  #endif /* CONFIG_MMU */
>
>  unsigned int riscv_cbom_block_size;
> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
>
>  #ifdef CONFIG_RISCV_ISA_ZICBOM
>  void riscv_init_cbom_blocksize(void)
> --
> 2.37.2
>


Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish

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Re: [PATCH v3 0/2] riscv: KVM: Expose Zicbom to the guest

[Conor.Dooley]

Hey Andrew,
Since Palmer declined the version of the Zicbom fixes with the relocation
of the block size, does this patch need a respin?
Thanks,
Conor.

On 09/09/2022 15:43, Andrew Jones wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Add support for exposing the Zicbom extension to guests. This has been
> tested over a QEMU including the Zicbom support [1] ([1] was rebased and
> the Zicboz support from it was dropped.) QEMU was further modified to
> ensure the cache block size was provided in the DT. kvmtool was also
> modified [2] to test the new KVM API and provide the guest the cache
> block size in its DT (The kvmtool patches are based on Anup's Svpbmt/Sstc
> series [3]). These KVM patches are based on the riscv_init_cbom_blocksize()
> cleanup patch from Palmer and the move and expose riscv_cbom_block_size
> patch from Anup which was reposted [4]. This series is also available here
> [5].
> 
> [1] https://gitlab.com/jones-drew/qemu/-/commits/riscv/zicbom
> [2] https://github.com/jones-drew/kvmtool/commits/riscv/zicbom
> [3] https://github.com/avpatel/kvmtool/commits/riscv_svpbmt_sstc_v1
> [4] https://lore.kernel.org/linux-riscv/20220906074509.928865-1-ajones@ventanamicro.com/T/#u
> [5] https://github.com/jones-drew/linux/commits/riscv/kvm/zicbom-v3
> 
> Thanks,
> drew
> 
> v3:
>  - Added check to ensure the extension is enabled for
>    config.get(blocksz) [Atish and Anup]
>  - Opportunistically switched all extension checks in
>    kvm_riscv_vcpu_update_config() to riscv_isa_extension_available()
>    from its __ counterpart
>  - Picked up some r-b's
> 
> v2:
>  - Dropped a patch that output the cache block size to dmesg
> 
> Andrew Jones (2):
>   RISC-V: KVM: Provide UAPI for Zicbom block size
>   RISC-V: KVM: Expose Zicbom to the guest
> 
>  arch/riscv/include/uapi/asm/kvm.h |  2 ++
>  arch/riscv/kvm/vcpu.c             | 17 +++++++++++++++--
>  arch/riscv/mm/cacheflush.c        |  1 +
>  3 files changed, 18 insertions(+), 2 deletions(-)
> 
> --
> 2.37.2
> 

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Re: [PATCH v3 1/2] RISC-V: KVM: Provide UAPI for Zicbom block size

[Anup Patel]

On Fri, Sep 9, 2022 at 8:14 PM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> We're about to allow guests to use the Zicbom extension. KVM
> userspace needs to know the cache block size in order to
> properly advertise it to the guest. Provide a virtual config
> register for userspace to get it with the GET_ONE_REG API, but
> setting it cannot be supported, so disallow SET_ONE_REG.
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Rebased and queued this patch for Linux-6.1

Thanks,
Anup

> ---
>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>  arch/riscv/kvm/vcpu.c             | 8 ++++++++
>  arch/riscv/mm/cacheflush.c        | 1 +
>  3 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 7351417afd62..b9a4cf36be4b 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -48,6 +48,7 @@ struct kvm_sregs {
>  /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
>  struct kvm_riscv_config {
>         unsigned long isa;
> +       unsigned long zicbom_block_size;
>  };
>
>  /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index d0f08d5b4282..2ef33d5d94d1 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -18,6 +18,7 @@
>  #include <linux/fs.h>
>  #include <linux/kvm_host.h>
>  #include <asm/csr.h>
> +#include <asm/cacheflush.h>
>  #include <asm/hwcap.h>
>
>  const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
> @@ -254,6 +255,11 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
>         case KVM_REG_RISCV_CONFIG_REG(isa):
>                 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> +               if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM))
> +                       return -EINVAL;
> +               reg_val = riscv_cbom_block_size;
> +               break;
>         default:
>                 return -EINVAL;
>         }
> @@ -311,6 +317,8 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
>                         return -EOPNOTSUPP;
>                 }
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> +               return -EOPNOTSUPP;
>         default:
>                 return -EINVAL;
>         }
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index e5b087be1577..f318b2553612 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -90,6 +90,7 @@ void flush_icache_pte(pte_t pte)
>  #endif /* CONFIG_MMU */
>
>  unsigned int riscv_cbom_block_size;
> +EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
>
>  #ifdef CONFIG_RISCV_ISA_ZICBOM
>  void riscv_init_cbom_blocksize(void)
> --
> 2.37.2
>

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Re: [PATCH v3 2/2] RISC-V: KVM: Expose Zicbom to the guest

[Anup Patel]

On Sat, Sep 10, 2022 at 12:07 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Fri, Sep 9, 2022 at 7:44 AM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > Guests may use the cbo.inval,clean,flush instructions when the
> > CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
> > (for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).
> >
> > Add Zicbom support for KVM guests which may be enabled and
> > disabled from KVM userspace using the ISA extension ONE_REG API.
> >
> > Also opportunistically switch the other isa extension checks in
> > kvm_riscv_vcpu_update_config() to riscv_isa_extension_available().
> >
> > Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Atish Patra <atishp@rivosinc.com>
> > ---
> >  arch/riscv/include/uapi/asm/kvm.h | 1 +
> >  arch/riscv/kvm/vcpu.c             | 9 +++++++--
> >  2 files changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > index b9a4cf36be4b..ed37a4a6e5cf 100644
> > --- a/arch/riscv/include/uapi/asm/kvm.h
> > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > @@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
> >         KVM_RISCV_ISA_EXT_M,
> >         KVM_RISCV_ISA_EXT_SVPBMT,
> >         KVM_RISCV_ISA_EXT_SSTC,
> > +       KVM_RISCV_ISA_EXT_ZICBOM,
> >         KVM_RISCV_ISA_EXT_MAX,
> >  };
> >
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 2ef33d5d94d1..74d1532b26c0 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
> >         RISCV_ISA_EXT_m,
> >         RISCV_ISA_EXT_SVPBMT,
> >         RISCV_ISA_EXT_SSTC,
> > +       RISCV_ISA_EXT_ZICBOM,
> >  };
> >
> >  static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
> > @@ -792,11 +793,15 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa)
> >  {
> >         u64 henvcfg = 0;
> >
> > -       if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SVPBMT))
> > +       if (riscv_isa_extension_available(isa, SVPBMT))
> >                 henvcfg |= ENVCFG_PBMTE;
> >
> > -       if (__riscv_isa_extension_available(isa, RISCV_ISA_EXT_SSTC))
> > +       if (riscv_isa_extension_available(isa, SSTC))
> >                 henvcfg |= ENVCFG_STCE;
> > +
>
> Ideally, these should be in a separate patch.
>
> > +       if (riscv_isa_extension_available(isa, ZICBOM))
> > +               henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
> > +
> >         csr_write(CSR_HENVCFG, henvcfg);
> >  #ifdef CONFIG_32BIT
> >         csr_write(CSR_HENVCFGH, henvcfg >> 32);
> > --
> > 2.37.2
> >
>
> Otherwise, LGTM.
> Reviewed-by: Atish Patra <atishp@rivosinc.com>

I agree with Atish's comment but this being a very simple change, I
have queued it as-is for Linux-6.1

Thanks,
Anup

> --
> Regards,
> Atish

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