From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: [PATCH v2 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC
Date: Mon, 27 Nov 2023 09:16:22 +0800 [thread overview]
Message-ID: <70ad5faa3a4a012df328fa21e69eaffd377e99ca.1701044106.git.unicorn_wang@outlook.com> (raw)
In-Reply-To: <cover.1701044106.git.unicorn_wang@outlook.com>
From: Chen Wang <unicorn_wang@outlook.com>
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 +
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 77 +++++++++++++++++++
2 files changed, 81 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index 49b4b9c2c101..0b3b3b2b0c64 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -14,6 +14,10 @@ chosen {
};
};
+&cgi {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..c5849a0e74d0 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo-sg2042-clk.h>
#include "sg2042-cpus.dtsi"
@@ -18,6 +19,12 @@ aliases {
serial0 = &uart0;
};
+ cgi: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -311,12 +318,82 @@ intc: interrupt-controller@7090000000 {
riscv,ndev = <224>;
};
+ sys_ctrl: syscon@7030010000 {
+ compatible = "sophgo,sg2042-syscon", "syscon";
+ reg = <0x70 0x30010000 0x0 0x8000>;
+
+ clkgen: clock-controller {
+ compatible = "sophgo,sg2042-clkgen";
+ #clock-cells = <1>;
+ clocks = <&cgi>;
+ assigned-clocks = \
+ <&clkgen DIV_CLK_FPLL_RP_CPU_NORMAL_1>,
+ <&clkgen DIV_CLK_FPLL_50M_A53>,
+ <&clkgen DIV_CLK_FPLL_TOP_RP_CMN_DIV2>,
+ <&clkgen DIV_CLK_FPLL_UART_500M>,
+ <&clkgen DIV_CLK_FPLL_AHB_LPC>,
+ <&clkgen DIV_CLK_FPLL_EFUSE>,
+ <&clkgen DIV_CLK_FPLL_TX_ETH0>,
+ <&clkgen DIV_CLK_FPLL_PTP_REF_I_ETH0>,
+ <&clkgen DIV_CLK_FPLL_REF_ETH0>,
+ <&clkgen DIV_CLK_FPLL_EMMC>,
+ <&clkgen DIV_CLK_FPLL_SD>,
+ <&clkgen DIV_CLK_FPLL_TOP_AXI0>,
+ <&clkgen DIV_CLK_FPLL_TOP_AXI_HSPERI>,
+ <&clkgen DIV_CLK_FPLL_AXI_DDR_1>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER1>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER2>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER3>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER4>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER5>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER6>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER7>,
+ <&clkgen DIV_CLK_FPLL_DIV_TIMER8>,
+ <&clkgen DIV_CLK_FPLL_100K_EMMC>,
+ <&clkgen DIV_CLK_FPLL_100K_SD>,
+ <&clkgen DIV_CLK_FPLL_GPIO_DB>,
+ <&clkgen DIV_CLK_MPLL_RP_CPU_NORMAL_0>,
+ <&clkgen DIV_CLK_MPLL_AXI_DDR_0>;
+ assigned-clock-rates = \
+ <2000000000>,
+ <50000000>,
+ <1000000000>,
+ <500000000>,
+ <200000000>,
+ <25000000>,
+ <125000000>,
+ <50000000>,
+ <25000000>,
+ <100000000>,
+ <100000000>,
+ <100000000>,
+ <250000000>,
+ <1000000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <50000000>,
+ <100000>,
+ <100000>,
+ <100000>,
+ <2000000000>,
+ <1000000000>;
+ };
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
--
2.25.1
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prev parent reply other threads:[~2023-11-27 1:16 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 0:57 [PATCH v2 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2023-11-27 0:58 ` [PATCH v2 1/4] dt-bindings: clock: sophgo: Add SG2042 bindings Chen Wang
2023-11-27 7:08 ` Krzysztof Kozlowski
2023-11-27 0:58 ` [PATCH v2 2/4] dt-bindings: soc: sophgo: Add Sophgo syscon module Chen Wang
2023-11-27 7:09 ` Krzysztof Kozlowski
2023-11-27 1:15 ` [PATCH v2 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2023-11-27 7:12 ` Krzysztof Kozlowski
2023-11-27 8:07 ` Chen Wang
2023-11-27 9:16 ` Krzysztof Kozlowski
2023-11-30 6:37 ` Chen Wang
2023-11-30 8:01 ` Krzysztof Kozlowski
2023-11-30 11:42 ` Chen Wang
2023-11-30 8:12 ` Conor Dooley
2023-11-30 11:32 ` Chen Wang
2023-11-27 1:16 ` Chen Wang [this message]
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