From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Chen Wang <unicornxw@gmail.com>,
aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
palmer@dabbelt.com, paul.walmsley@sifive.com,
richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com,
guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com,
samuel.holland@sifive.com
Cc: Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH v2 1/4] dt-bindings: clock: sophgo: Add SG2042 bindings
Date: Mon, 27 Nov 2023 08:08:06 +0100 [thread overview]
Message-ID: <e74740c2-7d61-4dfe-ae88-4ead6d72ea5a@linaro.org> (raw)
In-Reply-To: <aea19fcddcb0aec54b2779fc99b5ac6c1e465fe0.1701044106.git.unicorn_wang@outlook.com>
On 27/11/2023 01:58, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add bindings for the clock generator on the SG2042 RISC-V SoC.
>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> .../clock/sophgo/sophgo,sg2042-clkgen.yaml | 42 +++++
> include/dt-bindings/clock/sophgo-sg2042-clk.h | 169 ++++++++++++++++++
> 2 files changed, 211 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> create mode 100644 include/dt-bindings/clock/sophgo-sg2042-clk.h
>
> diff --git a/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> new file mode 100644
> index 000000000000..6c0d0461e489
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/sophgo/sophgo,sg2042-clkgen.yaml
> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/sophgo/sophgo,sg2042-clkgen.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SG2042 Clock Generator
> +
> +maintainers:
> + - Chen Wang <unicorn_wang@outlook.com>
> +
> +properties:
> + compatible:
> + const: sophgo,sg2042-clkgen
> +
> + clocks:
> + items:
> + - description: Clock Generation IC (25 MHz)
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/sophgo-sg2042-clk.h> for valid indices.
> +
> + assigned-clocks: true
Drop
> +
> + assigned-clock-rates: true
Drop
> +
> +required:
> + - compatible
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller {
> + compatible = "sophgo,sg2042-clkgen";
Use 4 spaces for example indentation.
> + clocks = <&cgi>;
> + #clock-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/sophgo-sg2042-clk.h b/include/dt-bindings/clock/sophgo-sg2042-clk.h
> new file mode 100644
> index 000000000000..a8e05c00c3bf
> --- /dev/null
> +++ b/include/dt-bindings/clock/sophgo-sg2042-clk.h
The same filename as binding.
> @@ -0,0 +1,169 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
Any particular reason for a bit different license than the bindings? How
is your DTS licensed?
> +/*
> + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
> +#define __DT_BINDINGS_CLOCK_SOPHGO_SG2042_H__
> +
> +/* Divider clocks */
> +#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0
Missing tabs before each value.
Best regards,
Krzysztof
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next prev parent reply other threads:[~2023-11-27 7:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 0:57 [PATCH v2 0/4] riscv: sophgo: add clock support for sg2042 Chen Wang
2023-11-27 0:58 ` [PATCH v2 1/4] dt-bindings: clock: sophgo: Add SG2042 bindings Chen Wang
2023-11-27 7:08 ` Krzysztof Kozlowski [this message]
2023-11-27 0:58 ` [PATCH v2 2/4] dt-bindings: soc: sophgo: Add Sophgo syscon module Chen Wang
2023-11-27 7:09 ` Krzysztof Kozlowski
2023-11-27 1:15 ` [PATCH v2 3/4] clk: sophgo: Add SG2042 clock generator driver Chen Wang
2023-11-27 7:12 ` Krzysztof Kozlowski
2023-11-27 8:07 ` Chen Wang
2023-11-27 9:16 ` Krzysztof Kozlowski
2023-11-30 6:37 ` Chen Wang
2023-11-30 8:01 ` Krzysztof Kozlowski
2023-11-30 11:42 ` Chen Wang
2023-11-30 8:12 ` Conor Dooley
2023-11-30 11:32 ` Chen Wang
2023-11-27 1:16 ` [PATCH v2 4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC Chen Wang
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