[RESEND v6 0/2] StarFive's SDIO/eMMC driver support

[RESEND v6 0/2] StarFive's SDIO/eMMC driver support

[William Qiu]

Hi,

This patchset adds initial rudimentary support for the StarFive
designware mobile storage host controller driver. And this driver will
be used in StarFive's VisionFive 2 board. The main purpose of adding
this driver is to accommodate the ultra-high speed mode of eMMC.

The last patch should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/

Changes v5->v6:
- Rebased to 6.3-rc1.
- Changed file name to starfive,jh7110.yaml.
- Modified commit description.
- Added syscon node dts patch to other dependent modules.

Changes v4->v5:
- Added a incremental updates to fix a bug that prev_err is uninitialized.
- Dropped the merged patches.
- Dropped the dts patch.
- Sorted compatible alphabetically in yaml.

Changes v3->v4:
- Added documentation to describe StarFive System Controller Registers.
- Added aon_syscon and stg_syscon node.
- Fixed some checkpatch errors/warnings.

Changes v2->v3:
- Wraped commit message according to Linux coding style.
- Rephrased the description of the patches.
- Changed the description of syscon regsiter.
- Dropped redundant properties.

Changes v1->v2:
- Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
- Changed the type of 'starfive,syscon' and modify its description.
- Deleted unused head files like '#include <linux/gpio.h>'.
- Added comment for the 'rise_point' and 'fall_point'.
- Changed the API 'num_caps' to 'common_caps'.
- Changed the node name 'sys_syscon' to 'syscon'.
- Changed the node name 'sdio' to 'mmc'.

The patch series is based on v6.3.

William Qiu (2):
  dt-bindings: soc: starfive: Add StarFive syscon doc
  riscv: dts: starfive: Add syscon node

 .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
 MAINTAINERS                                   |  5 +++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 15 +++++++
 3 files changed, 61 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml

--
2.34.1


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[RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

Add documentation to describe StarFive System Controller Registers.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
 MAINTAINERS                                   |  5 +++
 2 files changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..ae7f1d6916af
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+  - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+  The StarFive JH7110 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - starfive,jh7110-aon-syscon
+          - starfive,jh7110-stg-syscon
+          - starfive,jh7110-sys-syscon
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@10240000 {
+        compatible = "starfive,jh7110-stg-syscon", "syscon";
+        reg = <0x10240000 0x1000>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 958b7ec118b4..fdad60cc9f2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19964,6 +19964,11 @@ S:	Supported
 F:	Documentation/devicetree/bindings/rng/starfive*
 F:	drivers/char/hw_random/jh7110-trng.c

+STARFIVE JH7110 SYSCON
+M:	William Qiu <william.qiu@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
--
2.34.1


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[RESEND v6 2/2] riscv: dts: starfive: Add syscon node

[William Qiu]

Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..49dd62276b0d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -362,6 +362,11 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};

+		stg_syscon: syscon@10240000 {
+			compatible = "starfive,jh7110-stg-syscon", "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -466,6 +471,11 @@ syscrg: clock-controller@13020000 {
 			#reset-cells = <1>;
 		};

+		sys_syscon: syscon@13030000 {
+			compatible = "starfive,jh7110-sys-syscon", "syscon";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		sysgpio: pinctrl@13040000 {
 			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -495,6 +505,11 @@ aoncrg: clock-controller@17000000 {
 			#reset-cells = <1>;
 		};

+		aon_syscon: syscon@17010000 {
+			compatible = "starfive,jh7110-aon-syscon", "syscon";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
 		aongpio: pinctrl@17020000 {
 			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
--
2.34.1


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Re: [RESEND v6 2/2] riscv: dts: starfive: Add syscon node

[Conor Dooley]

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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Conor Dooley]

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On Wed, Mar 15, 2023 at 01:58:12PM +0800, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>

I thought I'd already left an R-b tag against this, but w/e, here it is
again:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

I'll pick this one up once either Krzysztof or Rob have reviewed it.

Cheers,
Conor.

> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>  MAINTAINERS                                   |  5 +++
>  2 files changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> +  - William Qiu <william.qiu@starfivetech.com>
> +
> +description: |
> +  The StarFive JH7110 SoC system controller provides register information such
> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - starfive,jh7110-aon-syscon
> +          - starfive,jh7110-stg-syscon
> +          - starfive,jh7110-sys-syscon
> +      - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    syscon@10240000 {
> +        compatible = "starfive,jh7110-stg-syscon", "syscon";
> +        reg = <0x10240000 0x1000>;
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 958b7ec118b4..fdad60cc9f2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19964,6 +19964,11 @@ S:	Supported
>  F:	Documentation/devicetree/bindings/rng/starfive*
>  F:	drivers/char/hw_random/jh7110-trng.c
> 
> +STARFIVE JH7110 SYSCON
> +M:	William Qiu <william.qiu@starfivetech.com>
> +S:	Supported
> +F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +
>  STATIC BRANCH/CALL
>  M:	Peter Zijlstra <peterz@infradead.org>
>  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> --
> 2.34.1
> 

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Re: [RESEND v6 2/2] riscv: dts: starfive: Add syscon node

[Emil Renner Berthing]

On Wed, 15 Mar 2023 at 06:58, William Qiu <william.qiu@starfivetech.com> wrote:
>
> Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>

> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index d484ecdf93f7..49dd62276b0d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -362,6 +362,11 @@ i2c2: i2c@10050000 {
>                         status = "disabled";
>                 };
>
> +               stg_syscon: syscon@10240000 {
> +                       compatible = "starfive,jh7110-stg-syscon", "syscon";
> +                       reg = <0x0 0x10240000 0x0 0x1000>;
> +               };
> +
>                 uart3: serial@12000000 {
>                         compatible = "snps,dw-apb-uart";
>                         reg = <0x0 0x12000000 0x0 0x10000>;
> @@ -466,6 +471,11 @@ syscrg: clock-controller@13020000 {
>                         #reset-cells = <1>;
>                 };
>
> +               sys_syscon: syscon@13030000 {
> +                       compatible = "starfive,jh7110-sys-syscon", "syscon";
> +                       reg = <0x0 0x13030000 0x0 0x1000>;
> +               };
> +
>                 sysgpio: pinctrl@13040000 {
>                         compatible = "starfive,jh7110-sys-pinctrl";
>                         reg = <0x0 0x13040000 0x0 0x10000>;
> @@ -495,6 +505,11 @@ aoncrg: clock-controller@17000000 {
>                         #reset-cells = <1>;
>                 };
>
> +               aon_syscon: syscon@17010000 {
> +                       compatible = "starfive,jh7110-aon-syscon", "syscon";
> +                       reg = <0x0 0x17010000 0x0 0x1000>;
> +               };
> +
>                 aongpio: pinctrl@17020000 {
>                         compatible = "starfive,jh7110-aon-pinctrl";
>                         reg = <0x0 0x17020000 0x0 0x10000>;
> --
> 2.34.1
>

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Krzysztof Kozlowski]

On 15/03/2023 06:58, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>  MAINTAINERS                                   |  5 +++
>  2 files changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> +  - William Qiu <william.qiu@starfivetech.com>
> +
> +description: |
> +  The StarFive JH7110 SoC system controller provides register information such
> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - starfive,jh7110-aon-syscon
> +          - starfive,jh7110-stg-syscon
> +          - starfive,jh7110-sys-syscon
> +      - const: syscon

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

... or your PLL clock controller was not tested.

Best regards,
Krzysztof


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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Krzysztof Kozlowski]

On 15/03/2023 06:58, William Qiu wrote:
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>  MAINTAINERS                                   |  5 +++
>  2 files changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..ae7f1d6916af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller

OK, I found the patch changing this. So basically you add knowingly
incomplete bindings and a second later you fix them.

Add complete bindings.

Best regards,
Krzysztof


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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
> On 15/03/2023 06:58, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>> 
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>>  MAINTAINERS                                   |  5 +++
>>  2 files changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..ae7f1d6916af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,41 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
>> +
>> +maintainers:
>> +  - William Qiu <william.qiu@starfivetech.com>
>> +
>> +description: |
>> +  The StarFive JH7110 SoC system controller provides register information such
>> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - enum:
>> +          - starfive,jh7110-aon-syscon
>> +          - starfive,jh7110-stg-syscon
>> +          - starfive,jh7110-sys-syscon
>> +      - const: syscon
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> 
> ... or your PLL clock controller was not tested.
> 
> Best regards,
> Krzysztof
> 
Hi Krzysztof,

I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
was not tested which I didn't add in this patch series. And PLL clock controller belongs
to Xingyu Wu, I would tell him.

Best regards
William

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

On 2023/3/19 20:29, Krzysztof Kozlowski wrote:
> On 15/03/2023 06:58, William Qiu wrote:
>> Add documentation to describe StarFive System Controller Registers.
>> 
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>>  MAINTAINERS                                   |  5 +++
>>  2 files changed, 46 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> new file mode 100644
>> index 000000000000..ae7f1d6916af
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> @@ -0,0 +1,41 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 SoC system controller
> 
> OK, I found the patch changing this. So basically you add knowingly
> incomplete bindings and a second later you fix them.
> 
> Add complete bindings.
> 
> Best regards,
> Krzysztof
> 
Originally, I only wanted to add a base module, and the binding of other modules
was added as incremental updates by other related colleagues. So now I need to
add the complete binding, right?

Best regards,
William

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Krzysztof Kozlowski]

On 20/03/2023 06:54, William Qiu wrote:
> 
> 
> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>> On 15/03/2023 06:58, William Qiu wrote:
>>> Add documentation to describe StarFive System Controller Registers.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> ---
>>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>>>  MAINTAINERS                                   |  5 +++
>>>  2 files changed, 46 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> new file mode 100644
>>> index 000000000000..ae7f1d6916af
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> @@ -0,0 +1,41 @@
>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: StarFive JH7110 SoC system controller
>>> +
>>> +maintainers:
>>> +  - William Qiu <william.qiu@starfivetech.com>
>>> +
>>> +description: |
>>> +  The StarFive JH7110 SoC system controller provides register information such
>>> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - enum:
>>> +          - starfive,jh7110-aon-syscon
>>> +          - starfive,jh7110-stg-syscon
>>> +          - starfive,jh7110-sys-syscon
>>> +      - const: syscon
>>
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>> ... or your PLL clock controller was not tested.
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
> 
> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
> was not tested which I didn't add in this patch series. And PLL clock controller belongs
> to Xingyu Wu, I would tell him.

What's confusing you do not allow here clock controller.

Best regards,
Krzysztof


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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Krzysztof Kozlowski]

On 20/03/2023 07:00, William Qiu wrote:
>>
> Originally, I only wanted to add a base module, and the binding of other modules
> was added as incremental updates by other related colleagues. So now I need to
> add the complete binding, right?

Binding should be complete.

Best regards,
Krzysztof


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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

On 2023/3/20 14:38, Krzysztof Kozlowski wrote:
> On 20/03/2023 07:00, William Qiu wrote:
>>>
>> Originally, I only wanted to add a base module, and the binding of other modules
>> was added as incremental updates by other related colleagues. So now I need to
>> add the complete binding, right?
> 
> Binding should be complete.
> 
> Best regards,
> Krzysztof
> 

I'll add it then.

Best regards
William

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

On 2023/3/20 14:38, Krzysztof Kozlowski wrote:
> On 20/03/2023 06:54, William Qiu wrote:
>> 
>> 
>> On 2023/3/19 20:27, Krzysztof Kozlowski wrote:
>>> On 15/03/2023 06:58, William Qiu wrote:
>>>> Add documentation to describe StarFive System Controller Registers.
>>>>
>>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> ---
>>>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 41 +++++++++++++++++++
>>>>  MAINTAINERS                                   |  5 +++
>>>>  2 files changed, 46 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> new file mode 100644
>>>> index 000000000000..ae7f1d6916af
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> @@ -0,0 +1,41 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: StarFive JH7110 SoC system controller
>>>> +
>>>> +maintainers:
>>>> +  - William Qiu <william.qiu@starfivetech.com>
>>>> +
>>>> +description: |
>>>> +  The StarFive JH7110 SoC system controller provides register information such
>>>> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    items:
>>>> +      - enum:
>>>> +          - starfive,jh7110-aon-syscon
>>>> +          - starfive,jh7110-stg-syscon
>>>> +          - starfive,jh7110-sys-syscon
>>>> +      - const: syscon
>>>
>>> Does not look like you tested the bindings. Please run `make
>>> dt_binding_check` (see
>>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>>
>>> ... or your PLL clock controller was not tested.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>> 
>> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
>> was not tested which I didn't add in this patch series. And PLL clock controller belongs
>> to Xingyu Wu, I would tell him.
> 
> What's confusing you do not allow here clock controller.
> 
> Best regards,
> Krzysztof
> 
I'll add it then.

Best regards
William

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 934 bytes --]

On Mon, Mar 20, 2023 at 03:32:14PM +0800, William Qiu wrote:

> >>> Does not look like you tested the bindings. Please run `make
> >>> dt_binding_check` (see
> >>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> >>>
> >>> ... or your PLL clock controller was not tested.
> >>>
> >>> Best regards,
> >>> Krzysztof
> >>>
> >> Hi Krzysztof,
> >> 
> >> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
> >> was not tested which I didn't add in this patch series. And PLL clock controller belongs
> >> to Xingyu Wu, I would tell him.
> > 
> > What's confusing you do not allow here clock controller.

> I'll add it then.

What's the plan here William?
Can you sort something out with Xingyu Wu so that the dt-binding is
added in a complete manner?
In the meantime, gonna drop this series as "Changes Requested" from
patchwork.

Cheers,
Conor.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [RESEND v6 1/2] dt-bindings: soc: starfive: Add StarFive syscon doc

[William Qiu]

On 2023/4/6 0:38, Conor Dooley wrote:
> On Mon, Mar 20, 2023 at 03:32:14PM +0800, William Qiu wrote:
> 
>> >>> Does not look like you tested the bindings. Please run `make
>> >>> dt_binding_check` (see
>> >>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>> >>>
>> >>> ... or your PLL clock controller was not tested.
>> >>>
>> >>> Best regards,
>> >>> Krzysztof
>> >>>
>> >> Hi Krzysztof,
>> >> 
>> >> I've already done`make dt_binding_check`, and get no error. So maybe PLL clock controller
>> >> was not tested which I didn't add in this patch series. And PLL clock controller belongs
>> >> to Xingyu Wu, I would tell him.
>> > 
>> > What's confusing you do not allow here clock controller.
> 
>> I'll add it then.
> 
> What's the plan here William?
> Can you sort something out with Xingyu Wu so that the dt-binding is
> added in a complete manner?
> In the meantime, gonna drop this series as "Changes Requested" from
> patchwork.
> 
> Cheers,
> Conor.

Hi Conor,

After discussing with Xingyu, I will sort all of it and send a complete
dt-binding today.

Best regards,
William

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