messages from 2019-03-22 10:42:28 to 2019-03-29 19:41:27 UTC [more...]
[PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed
2019-03-29 19:41 UTC (13+ messages)
` [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller
` [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
[PATCH] riscv: fix syscall_get_arguments() and syscall_set_arguments()
2019-03-29 18:16 UTC (6+ messages)
[PATCH] RISC-V: Use IS_ENABLED(CONFIG_CMODEL_MEDLOW)
2019-03-29 7:41 UTC (2+ messages)
[PATCH] RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area
2019-03-29 7:08 UTC (6+ messages)
[PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address
2019-03-28 15:35 UTC
[PATCH v2] RISC-V: Implement ASID allocator
2019-03-29 5:12 UTC (10+ messages)
[PATCH v3] RISC-V: Implement ASID allocator
2019-03-29 4:51 UTC
[RFC][PATCH 3/4 v2] syscalls: Remove start and number from syscall_get_arguments() args
2019-03-28 23:05 UTC (2+ messages)
` [RFC][PATCH 4/4 v2] syscalls: Remove start and number from syscall_set_arguments() args
[PATCH 0/7] RISC-V: Sparsmem, Memory Hotplug and pte_devmap for P2P
2019-03-28 18:24 UTC (15+ messages)
` [PATCH 1/7] RISC-V: Implement sparsemem
` [PATCH 2/7] RISC-V: doc: Add file describing the virtual memory map
` [PATCH 3/7] RISC-V: Rework kernel's virtual address space mapping
` [PATCH 4/7] RISC-V: Update page tables to cover the whole linear mapping
` [PATCH 5/7] RISC-V: Implement memory hotplug
` [PATCH 6/7] RISC-V: Implement memory hot remove
` [PATCH 7/7] RISC-V: Implement pte_devmap()
[PATCH v4 0/5] TLB/I$ flush cleanups and improvements
2019-03-28 16:57 UTC (24+ messages)
` [PATCH v4 1/5] riscv: move flush_icache_{all,mm} to cacheflush.c
` [PATCH v4 3/5] riscv: fix sbi_remote_sfence_vma{,_asid}
` [PATCH v4 2/5] riscv: move switch_mm to its own file
` [PATCH v4 4/5] riscv: rewrite tlb flush for performance
` [PATCH v4 5/5] riscv: implement IPI-based remote TLB shootdown
[PATCH v7 06/20] riscv: mm: Add p?d_large() definitions
2019-03-28 15:20 UTC
[PATCH v3 0/4] Boot RISC-V kernel from any 4KB aligned address
2019-03-28 10:24 UTC (20+ messages)
` [PATCH v3 1/4] RISC-V: Add separate defconfig for 32bit systems
` [PATCH v3 2/4] RISC-V: Fix memory reservation in setup_bootmem()
` [PATCH v3 3/4] RISC-V: Remove redundant trampoline page table
` [PATCH v3 4/4] RISC-V: Allow booting kernel from any 4KB aligned address
[PATCH] RISC-V: Implement ASID allocator
2019-03-27 14:12 UTC (9+ messages)
[PATCH v11 0/2] PWM support for HiFive Unleashed
2019-03-27 9:04 UTC (7+ messages)
` [PATCH v11 1/2] pwm: sifive: Add DT documentation for SiFive PWM Controller
` [PATCH v11 2/2] pwm: sifive: Add a driver for SiFive SoC PWM
[PATCH v2] RISC-V: Always compile mm/init.c with cmodel=medany
2019-03-27 0:10 UTC (9+ messages)
[PATCH] irqchip: plic: Fix priority base offset
2019-03-26 22:26 UTC (5+ messages)
[PATCH v6 05/19] riscv: mm: Add p?d_large() definitions
2019-03-26 16:26 UTC
[PATCH v4] RISC-V: Always compile mm/init.c with cmodel=medany and notrace
2019-03-26 8:03 UTC
Thoughts on kexec / SBI
2019-03-26 6:57 UTC (5+ messages)
[PATCH 5.0 29/52] clocksource/drivers/riscv: Fix clocksource mask
2019-03-26 6:30 UTC
[PATCH v3] RISC-V: Always compile mm/init.c with cmodel=medany and notrace
2019-03-26 3:57 UTC (3+ messages)
[PATCH 0/2] EDAC Support for SiFive SoCs
2019-03-25 21:50 UTC (8+ messages)
` [PATCH 1/2] edac: sifive: Add DT documentation for SiFive EDAC driver and subcomponent
` [PATCH 2/2] edac: sifive: Add EDAC driver for SiFive FU540-C000 chip
[PATCH 0/3] RISC-V SBI earlycon
2019-03-25 16:23 UTC (2+ messages)
[PATCH v5 0/3] locking/rwsem: Rwsem rearchitecture part 0
2019-03-25 15:25 UTC (13+ messages)
` [PATCH v5 1/3] locking/rwsem: Remove arch specific rwsem files
` [PATCH v5 2/3] locking/rwsem: Remove rwsem-spinlock.c & use rwsem-xadd.c for all archs
` [PATCH v5 3/3] locking/rwsem: Optimize down_read_trylock()
[PATCH v9 0/2] PWM support for HiFive Unleashed
2019-03-25 12:09 UTC (8+ messages)
[PATCH v2 0/4] provide a generic free_initmem implementation
2019-03-25 7:20 UTC (2+ messages)
[PATCH v2 0/5] Boot RISC-V kernel from any 4KB aligned address
2019-03-25 4:19 UTC (15+ messages)
` [PATCH v2 2/5] RISC-V: Make setup_vm() independent of GCC code model
` [PATCH v2 3/5] RISC-V: Allow booting kernel from any 4KB aligned address
` [PATCH v2 4/5] RISC-V: Remove redundant trampoline page table
` [PATCH v2 5/5] RISC-V: Fix memory reservation in setup_bootmem()
[PATCH] RISC-V: Always compile mm/init.c with cmodel=medany
2019-03-25 3:21 UTC (7+ messages)
[RFT/RFC PATCH v3 0/5] Unify CPU topology across ARM & RISC-V
2019-03-24 21:16 UTC (3+ messages)
` [RFT/RFC PATCH v3 2/5] dt-binding: cpu-topology: Move cpu-map to a common binding
Patch "clocksource/drivers/riscv: Fix clocksource mask" has been added to the 5.0-stable tree
2019-03-24 20:15 UTC
32bit kernel is broken for Linux-5.1-rc1 due to GCC cmodel=medlow
2019-03-24 9:41 UTC (17+ messages)
[PATCH] clocksource/drivers/riscv: Fix clocksource mask
2019-03-23 11:15 UTC (2+ messages)
[PATCH 0/4] Provide generic top-down mmap layout functions
2019-03-23 8:18 UTC (7+ messages)
` [PATCH 1/4] arm64, mm: Move generic mmap layout functions to mm
` [PATCH 4/4] riscv: Make mmap allocation top-down by default
per-cpu thoughts
2019-03-22 17:57 UTC (8+ messages)
[PATCH] riscv: fix accessing 8-byte variable from RV32
2019-03-22 13:34 UTC (2+ messages)
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