* [PATCH] clocksource/drivers/riscv: Fix clocksource mask
@ 2019-03-22 21:54 Atish Patra
2019-03-23 11:15 ` Anup Patel
0 siblings, 1 reply; 2+ messages in thread
From: Atish Patra @ 2019-03-22 21:54 UTC (permalink / raw)
To: linux-kernel
Cc: Damien Le Moal, Albert Ou, Daniel Lezcano, Palmer Dabbelt,
Atish Patra, Anup Patel, linux-riscv, Thomas Gleixner
For all riscv architectures (RV32, RV64 and RV128), the clocksource
is a 64 bit incrementing counter.
Fix the clock source mask accordingly.
Tested on both 64bit and 32 bit virt machine in QEMU.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
drivers/clocksource/timer-riscv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index e8163693..5e6038fb 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void)
static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
.name = "riscv_clocksource",
.rating = 300,
- .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
+ .mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.read = riscv_clocksource_rdtime,
};
@@ -120,8 +120,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
return error;
}
- sched_clock_register(riscv_sched_clock,
- BITS_PER_LONG, riscv_timebase);
+ sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
"clockevents/riscv/timer:starting",
--
2.21.0
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^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clocksource/drivers/riscv: Fix clocksource mask
2019-03-22 21:54 [PATCH] clocksource/drivers/riscv: Fix clocksource mask Atish Patra
@ 2019-03-23 11:15 ` Anup Patel
0 siblings, 0 replies; 2+ messages in thread
From: Anup Patel @ 2019-03-23 11:15 UTC (permalink / raw)
To: Atish Patra
Cc: Damien Le Moal, Albert Ou, Daniel Lezcano,
linux-kernel@vger.kernel.org List, Anup Patel, Palmer Dabbelt,
linux-riscv, Thomas Gleixner
On Sat, Mar 23, 2019 at 3:24 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> For all riscv architectures (RV32, RV64 and RV128), the clocksource
> is a 64 bit incrementing counter.
>
> Fix the clock source mask accordingly.
>
> Tested on both 64bit and 32 bit virt machine in QEMU.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> drivers/clocksource/timer-riscv.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index e8163693..5e6038fb 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void)
> static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
> .name = "riscv_clocksource",
> .rating = 300,
> - .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
> + .mask = CLOCKSOURCE_MASK(64),
> .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> .read = riscv_clocksource_rdtime,
> };
> @@ -120,8 +120,7 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> return error;
> }
>
> - sched_clock_register(riscv_sched_clock,
> - BITS_PER_LONG, riscv_timebase);
> + sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
>
> error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
> "clockevents/riscv/timer:starting",
> --
> 2.21.0
>
Looks good to me.
It would be great if you can add "Fixes:" line and
"Cc: stable@vger.kernel.org"
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
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