Linux-RISC-V Archive on lore.kernel.org
 help / color / Atom feed
From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	Christoph Hellwig <hch@infradead.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base
Date: Fri, 30 Nov 2018 09:04:46 +0530
Message-ID: <CAAhSdy0CDxoV2qJ-Xh-4udhh_jEz2KWKPfC_5QSo79VRo4EwUg@mail.gmail.com> (raw)
In-Reply-To: <b6ff2593-9113-9b95-ade5-09e7e9fa1be5@wdc.com>

On Fri, Nov 30, 2018 at 6:05 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> On 11/27/18 2:03 AM, Anup Patel wrote:
> > This patch does following optimizations:
> > 1. Pre-compute hart base for each context handler
> > 2. Pre-compute enable base for each context handler
> > 3. Have enable lock for each context handler instead
> > of global plic_toggle_lock
> >
> > Signed-off-by: Anup Patel <anup@brainfault.org>
> > ---
> >   drivers/irqchip/irq-sifive-plic.c | 41 +++++++++++++------------------
> >   1 file changed, 17 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index 357e9daf94ae..56fce648a901 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -60,36 +60,24 @@ static void __iomem *plic_regs;
> >   struct plic_handler {
> >       bool                    present;
> >       int                     ctxid;
> > +     void __iomem            *hart_base;
> > +     raw_spinlock_t          enable_lock;
> > +     void __iomem            *enable_base;
>
> It should be u32. Otherwise, plic_toggle calculates incorrect address
> and it does not boot on Unlheased.

Good catch. I did not see this issue on QEMU because we have
very IRQs over there.

>
> >   };
> >   static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
> >
> > -static inline void __iomem *plic_hart_offset(int ctxid)
> > +static inline void plic_toggle(struct plic_handler *handler,
> > +                             int hwirq, int enable)
> >   {
> > -     return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
> > -}
> > -
> > -static inline u32 __iomem *plic_enable_base(int ctxid)
> > -{
> > -     return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
> > -}
> > -
> > -/*
> > - * Protect mask operations on the registers given that we can't assume that
> > - * atomic memory operations work on them.
> > - */
>
> Should we keep the comment for enable_lock ?

Sure, I will retain the comment for enable_lock.

>
> > -static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
> > -
> > -static inline void plic_toggle(int ctxid, int hwirq, int enable)
> > -{
> > -     u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
> > +     u32 __iomem *reg = handler->enable_base + (hwirq / 32);
> >       u32 hwirq_mask = 1 << (hwirq % 32);
> >
> > -     raw_spin_lock(&plic_toggle_lock);
> > +     raw_spin_lock(&handler->enable_lock);
> >       if (enable)
> >               writel(readl(reg) | hwirq_mask, reg);
> >       else
> >               writel(readl(reg) & ~hwirq_mask, reg);
> > -     raw_spin_unlock(&plic_toggle_lock);
> > +     raw_spin_unlock(&handler->enable_lock);
> >   }
> >
> >   static inline void plic_irq_toggle(struct irq_data *d, int enable)
> > @@ -101,7 +89,7 @@ static inline void plic_irq_toggle(struct irq_data *d, int enable)
> >               struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
> >
> >               if (handler->present)
> > -                     plic_toggle(handler->ctxid, d->hwirq, enable);
> > +                     plic_toggle(handler, d->hwirq, enable);
> >       }
> >   }
> >
> > @@ -150,7 +138,7 @@ static struct irq_domain *plic_irqdomain;
> >   static void plic_handle_irq(struct pt_regs *regs)
> >   {
> >       struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > -     void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
> > +     void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
> >       irq_hw_number_t hwirq;
> >
> >       WARN_ON_ONCE(!handler->present);
> > @@ -240,11 +228,16 @@ static int __init plic_init(struct device_node *node,
> >               handler = per_cpu_ptr(&plic_handlers, cpu);
> >               handler->present = true;
> >               handler->ctxid = i;
> > +             handler->hart_base =
> > +                     plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
> > +             raw_spin_lock_init(&handler->enable_lock);
> > +             handler->enable_base =
> > +                     plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
> >
> >               /* priority must be > threshold to trigger an interrupt */
> > -             writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
> > +             writel(0, handler->hart_base + CONTEXT_THRESHOLD);
> >               for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
> > -                     plic_toggle(i, hwirq, 0);
> > +                     plic_toggle(handler, hwirq, 0);
> >               nr_mapped++;
> >       }
> >
> >
>

--
Anup

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-27 10:03 [PATCH v2 0/4] IRQ affinity support in PLIC driver anup
2018-11-27 10:03 ` Anup Patel
2018-11-27 10:03 ` [PATCH v2 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base anup
2018-11-27 10:03   ` Anup Patel
2018-11-30  0:35   ` Atish Patra
2018-11-30  3:34     ` Anup Patel [this message]
2018-11-27 10:03 ` [PATCH v2 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle() anup
2018-11-27 10:03   ` Anup Patel
2018-11-30  1:39   ` Atish Patra
2018-11-30  3:51     ` Anup Patel
2018-11-27 10:03 ` [PATCH v2 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context anup
2018-11-27 10:03   ` Anup Patel
2018-11-30  1:57   ` Atish Patra
2018-11-30  3:55     ` Anup Patel
2018-11-27 10:03 ` [PATCH v2 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host anup
2018-11-27 10:03   ` Anup Patel
2018-11-30  5:59   ` Atish Patra
2018-11-30  7:51     ` Anup Patel
2018-11-30  7:54     ` Atish Patra

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAAhSdy0CDxoV2qJ-Xh-4udhh_jEz2KWKPfC_5QSo79VRo4EwUg@mail.gmail.com \
    --to=anup@brainfault.org \
    --cc="linux-kernel@vger.kernel.org \
    --cc=aou@eecs.berkeley.edu \
    --cc=atish.patra@wdc.com \
    --cc=daniel.lezcano@linaro.org \
    --cc=hch@infradead.org \
    --cc=jason@lakedaemon.net \
    --cc=linux-riscv@lists.infradead.org \
    --cc=marc.zyngier@arm.com \
    --cc=palmer@sifive.com \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-RISC-V Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-riscv/0 linux-riscv/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-riscv linux-riscv/ https://lore.kernel.org/linux-riscv \
		linux-riscv@lists.infradead.org infradead-linux-riscv@archiver.kernel.org
	public-inbox-index linux-riscv

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-riscv


AGPL code for this site: git clone https://public-inbox.org/ public-inbox