From: Guo Ren <guoren@kernel.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: "Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>,
wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
gordan.markus@canonical.com, "Guo Ren" <guoren@linux.alibaba.com>,
"Anup Patel" <anup@brainfault.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Rob Herring" <robh+dt@kernel.org>
Subject: Re: [PATCH V2 2/2] dt-bindings: riscv: Add svpbmt in cpu mmu-type property
Date: Tue, 28 Sep 2021 08:42:51 +0800 [thread overview]
Message-ID: <CAJF2gTSbPbVRYkhD5zaFT=UWKiRjj1-pxjfCVxL3AWgAiASp5A@mail.gmail.com> (raw)
In-Reply-To: <CAOnJCU+6hUSdviwCM6uwCQr=OV3xQP=RF-BmdJFY8Tzgd_L51Q@mail.gmail.com>
On Tue, Sep 28, 2021 at 3:32 AM Atish Patra <atishp@atishpatra.org> wrote:
>
>
>
> On Thu, Sep 23, 2021 at 10:22 AM <guoren@kernel.org> wrote:
>>
>> From: Guo Ren <guoren@linux.alibaba.com>
>>
>> Previous patch has added svpbmt in arch/riscv and changed the
>> DT mmu-type. Update dt-bindings related property here.
>>
>
> This is the first of many small ISA extensions to be added to RISC-V.
> Should we think about a generic DT property and parsing framework for all hart related ISA extensions now instead of adding
> to the existing mmu-type.
Change existing mmu-type will cause a compatible problem. If we still
keep current solution, I think it's still okay. eg:
mmu-type = "riscv,sv39,svpbmt,svnapot,svinval";
Or, if we still want to change, how:
mmu-type = "riscv,sv39";
mmu-type-ext = "svpbmt,svnapot,svinval"
Still keep mmu-type like before.
>
> We will soon need to add the CMO extensions as well.
>
>>
>> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
>> Cc: Anup Patel <anup@brainfault.org>
>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> ---
>> Documentation/devicetree/bindings/riscv/cpus.yaml | 9 ++++++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> index e534f6a7cfa1..5eea9b47dfc6 100644
>> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
>> @@ -48,15 +48,18 @@ properties:
>>
>> mmu-type:
>> description:
>> - Identifies the MMU address translation mode used on this
>> - hart. These values originate from the RISC-V Privileged
>> - Specification document, available from
>> + Identifies the MMU address translation mode and page based
>> + memory type used on used on this hart. These values originate
>> + from the RISC-V Privileged Specification document, available
>> + from
>> https://riscv.org/specifications/
>> $ref: "/schemas/types.yaml#/definitions/string"
>> enum:
>> - riscv,sv32
>> - riscv,sv39
>> + - riscv,sv39,svpbmt
>> - riscv,sv48
>> + - riscv,sv48,svpbmt
>> - riscv,none
>>
>> riscv,isa:
>> --
>> 2.25.1
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
>
> --
> Regards,
> Atish
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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next prev parent reply other threads:[~2021-09-28 0:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 17:21 [PATCH V2 1/2] riscv: Add RISC-V svpbmt extension guoren
2021-09-23 17:21 ` [PATCH V2 2/2] dt-bindings: riscv: Add svpbmt in cpu mmu-type property guoren
[not found] ` <CAOnJCU+6hUSdviwCM6uwCQr=OV3xQP=RF-BmdJFY8Tzgd_L51Q@mail.gmail.com>
2021-09-28 0:42 ` Guo Ren [this message]
[not found] ` <CAOnJCUJWnDB+uRxDh=YSbGW4bf5RQvke03iCTYMYHPsw3cwnHQ@mail.gmail.com>
2021-09-27 20:13 ` [PATCH V2 1/2] riscv: Add RISC-V svpbmt extension Atish Patra
[not found] ` <CA+Qh7T=kud8AM-6JjuWNwJY0r_gkmnP6SmzVXqeE2VYxViLUoQ@mail.gmail.com>
2021-09-27 23:05 ` Atish Patra
2021-09-28 9:45 ` Philipp Tomsich
2021-09-28 0:23 ` Nick Kossifidis
2021-09-28 1:02 ` Nick Kossifidis
2021-09-28 3:50 ` Anup Patel
2021-09-28 4:26 ` Atish Patra
2021-09-28 6:03 ` Guo Ren
[not found] ` <CA+Qh7T=p4+p0c8XF4YiVaCmc--HtjTLdn6=YNa4SBb8yZk2maA@mail.gmail.com>
2021-09-28 6:14 ` Atish Patra
2021-09-28 13:19 ` Nick Kossifidis
2021-09-28 13:46 ` Philipp Tomsich
2021-09-28 14:58 ` Alexandre Ghiti
2021-10-05 0:44 ` Palmer Dabbelt
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