From: Nick Kossifidis <mick@ics.forth.gr>
To: Greg Favor <gfavor@ventanamicro.com>
Cc: "Atish Patra" <atishp@atishpatra.org>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Guo Ren" <guoren@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>,
wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
gordan.markus@canonical.com, "Guo Ren" <guoren@linux.alibaba.com>,
"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [PATCH V2 1/2] riscv: Add RISC-V svpbmt extension
Date: Tue, 28 Sep 2021 03:23:37 +0300 [thread overview]
Message-ID: <ce3bb9f5c72f0feb1cf9a0d67edaedf6@mailhost.ics.forth.gr> (raw)
In-Reply-To: <CA+Qh7T=kud8AM-6JjuWNwJY0r_gkmnP6SmzVXqeE2VYxViLUoQ@mail.gmail.com>
Hello Greg,
Στις 2021-09-27 23:53, Greg Favor έγραψε:
> With the big caveat that I haven't been in the middle of this
> discussion, it seems like Allwinner D1's changes represent a custom
> (and nonconforming) extension. Isn't this just a matter of the patch
> needing to be treated as for a RISC-V custom extension per the recently
> clarified policy for handling upstreaming/etc. of custom extensions?
> (Philipp can speak to this clarified policy.) Or what am I missing?
>
The Priv. Spec. defines sv39/48 without allowing custom use of reserved
pte bits by implementations, Allwinner D1 claims to be sv39 but it does
use reserved PTE bits. When vendors want to do custom stuff on PTEs, the
standard says they may use values 14-15 on satp.mode for that and define
their own MMU basically. Messing up with the implementation of sv39 is
not an extension, is violation of sv39. Even worse this implementation
can't work if we ignore the customization since without setting the
required bits on PTEs dma (and I believe SMP as well) doesn't work.
Regards,
Nick
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next prev parent reply other threads:[~2021-09-28 0:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 17:21 [PATCH V2 1/2] riscv: Add RISC-V svpbmt extension guoren
2021-09-23 17:21 ` [PATCH V2 2/2] dt-bindings: riscv: Add svpbmt in cpu mmu-type property guoren
[not found] ` <CAOnJCU+6hUSdviwCM6uwCQr=OV3xQP=RF-BmdJFY8Tzgd_L51Q@mail.gmail.com>
2021-09-28 0:42 ` Guo Ren
[not found] ` <CAOnJCUJWnDB+uRxDh=YSbGW4bf5RQvke03iCTYMYHPsw3cwnHQ@mail.gmail.com>
2021-09-27 20:13 ` [PATCH V2 1/2] riscv: Add RISC-V svpbmt extension Atish Patra
[not found] ` <CA+Qh7T=kud8AM-6JjuWNwJY0r_gkmnP6SmzVXqeE2VYxViLUoQ@mail.gmail.com>
2021-09-27 23:05 ` Atish Patra
2021-09-28 9:45 ` Philipp Tomsich
2021-09-28 0:23 ` Nick Kossifidis [this message]
2021-09-28 1:02 ` Nick Kossifidis
2021-09-28 3:50 ` Anup Patel
2021-09-28 4:26 ` Atish Patra
2021-09-28 6:03 ` Guo Ren
[not found] ` <CA+Qh7T=p4+p0c8XF4YiVaCmc--HtjTLdn6=YNa4SBb8yZk2maA@mail.gmail.com>
2021-09-28 6:14 ` Atish Patra
2021-09-28 13:19 ` Nick Kossifidis
2021-09-28 13:46 ` Philipp Tomsich
2021-09-28 14:58 ` Alexandre Ghiti
2021-10-05 0:44 ` Palmer Dabbelt
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