From: Arnd Bergmann <arnd@kernel.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Guo Ren <guoren@linux.alibaba.com>, Arnd Bergmann <arnd@arndb.de>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmerdabbelt@google.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
linux-csky@vger.kernel.org, Michael Clark <michaeljclark@mac.com>,
Guo Ren <guoren@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported
Date: Tue, 24 Nov 2020 16:00:14 +0100 [thread overview]
Message-ID: <CAK8P3a1ykYmpXtjVbeAjLPY0AtfQTpL9jJ8e6SokiTb=J9UhnQ@mail.gmail.com> (raw)
In-Reply-To: <20201124143931.GI2414@hirez.programming.kicks-ass.net>
On Tue, Nov 24, 2020 at 3:39 PM Peter Zijlstra <peterz@infradead.org> wrote:
> On Tue, Nov 24, 2020 at 01:43:54PM +0000, guoren@kernel.org wrote:
> > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
> > + if (align) { \
> > + __asm__ __volatile__ ( \
> > + "0: lr.w %0, 0(%z4)\n" \
> > + " move %1, %0\n" \
> > + " slli %1, %1, 16\n" \
> > + " srli %1, %1, 16\n" \
> > + " move %2, %z3\n" \
> > + " slli %2, %2, 16\n" \
> > + " or %1, %2, %1\n" \
> > + " sc.w %2, %1, 0(%z4)\n" \
> > + " bnez %2, 0b\n" \
> > + " srli %0, %0, 16\n" \
> > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
> > + : "rJ" (__new), "rJ"(addr) \
> > + : "memory"); \
>
> I'm pretty sure there's a handfull of implementations like this out
> there... if only we could share.
Isn't this effectively the same as the "_Q_PENDING_BITS != 8"
version of xchg_tail()?
If nothing else needs xchg() on a 16-bit value, maybe
changing the #ifdef in the qspinlock code is enough.
Only around half the architectures actually implement 8-bit
and 16-bit cmpxchg() and xchg(), it might even be worth trying
to eventually change the interface to not do it at all, but
instead have explicit cmpxchg8() and cmpxchg16() helpers
for the few files that do use them.
Arnd
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next prev parent reply other threads:[~2020-11-24 15:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 13:43 [PATCH 1/5] riscv: Coding convention for xchg guoren
2020-11-24 13:43 ` [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported guoren
2020-11-24 14:39 ` Peter Zijlstra
2020-11-24 15:00 ` Arnd Bergmann [this message]
2020-11-25 14:09 ` Guo Ren
2020-11-25 14:16 ` Peter Zijlstra
2020-11-25 14:31 ` Will Deacon
2020-11-26 1:36 ` Guo Ren
2020-11-26 8:53 ` Will Deacon
2020-11-25 0:52 ` Guo Ren
2020-11-25 14:18 ` Peter Zijlstra
2020-11-24 13:43 ` [PATCH 3/5] csky: Remove simple spinlock implementation guoren
2020-11-24 13:43 ` [PATCH 4/5] csky: Add QUEUED_SPINLOCKS supported guoren
2020-11-24 13:43 ` [PATCH 5/5] csky: Optimize atomic operations with correct barrier usage guoren
2020-11-24 14:29 ` [PATCH 1/5] riscv: Coding convention for xchg Peter Zijlstra
2020-11-25 14:18 ` Guo Ren
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