From: Guo Ren <guoren@kernel.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Guo Ren <guoren@linux.alibaba.com>, Arnd Bergmann <arnd@arndb.de>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-csky@vger.kernel.org, Michael Clark <michaeljclark@mac.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported
Date: Wed, 25 Nov 2020 08:52:23 +0800 [thread overview]
Message-ID: <CAJF2gTTBbjOhvvLTd6d5zgb0kskoSJhPW7nmg==4w2wV+OaUgg@mail.gmail.com> (raw)
In-Reply-To: <20201124143931.GI2414@hirez.programming.kicks-ass.net>
Thx Peter,
On Tue, Nov 24, 2020 at 10:39 PM Peter Zijlstra <peterz@infradead.org> wrote:
>
> On Tue, Nov 24, 2020 at 01:43:54PM +0000, guoren@kernel.org wrote:
> > diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild
> > index 59dd7be..6f5f438 100644
> > --- a/arch/riscv/include/asm/Kbuild
> > +++ b/arch/riscv/include/asm/Kbuild
> > @@ -6,3 +6,6 @@ generic-y += kvm_para.h
> > generic-y += local64.h
> > generic-y += user.h
> > generic-y += vmlinux.lds.h
> > +generic-y += mcs_spinlock.h
> > +generic-y += qrwlock.h
> > +generic-y += qspinlock.h
> > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> > index 5609185..e178700 100644
> > --- a/arch/riscv/include/asm/cmpxchg.h
> > +++ b/arch/riscv/include/asm/cmpxchg.h
> > @@ -16,7 +16,43 @@
> > __typeof__(ptr) __ptr = (ptr); \
> > __typeof__(new) __new = (new); \
> > __typeof__(*(ptr)) __ret; \
> > + register unsigned long __rc, tmp, align, addr; \
> > switch (size) { \
> > + case 2: \
> > + align = ((unsigned long) __ptr & 0x3); \
> > + addr = ((unsigned long) __ptr & ~0x3); \
> > + if (align) { \
> > + __asm__ __volatile__ ( \
> > + "0: lr.w %0, 0(%z4)\n" \
> > + " move %1, %0\n" \
> > + " slli %1, %1, 16\n" \
> > + " srli %1, %1, 16\n" \
> > + " move %2, %z3\n" \
> > + " slli %2, %2, 16\n" \
> > + " or %1, %2, %1\n" \
> > + " sc.w %2, %1, 0(%z4)\n" \
> > + " bnez %2, 0b\n" \
> > + " srli %0, %0, 16\n" \
> > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
> > + : "rJ" (__new), "rJ"(addr) \
> > + : "memory"); \
> > + } else { \
> > + __asm__ __volatile__ ( \
> > + "0: lr.w %0, (%z4)\n" \
> > + " move %1, %0\n" \
> > + " srli %1, %1, 16\n" \
> > + " slli %1, %1, 16\n" \
> > + " move %2, %z3\n" \
> > + " or %1, %2, %1\n" \
> > + " sc.w %2, %1, 0(%z4)\n" \
> > + " bnez %2, 0b\n" \
> > + " slli %0, %0, 16\n" \
> > + " srli %0, %0, 16\n" \
> > + : "=&r" (__ret), "=&r" (tmp), "=&r" (__rc) \
> > + : "rJ" (__new), "rJ"(addr) \
> > + : "memory"); \
> > + } \
> > + break; \
> > case 4: \
> > __asm__ __volatile__ ( \
> > " amoswap.w %0, %2, %1\n" \
>
> I'm pretty sure there's a handfull of implementations like this out
> there... if only we could share.
Michael has sent qspinlock before, ref to Link below. He reused mips' code.
Link: https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/
Which short xchg implementation do you prefer (Mine or his)?
>
> Anyway, this too should be an independent patch.
Ok, I'll separate it into two patches,
1. implement short xchg
2. qspinlock enabled based on Michael's patch
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
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next prev parent reply other threads:[~2020-11-25 0:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 13:43 [PATCH 1/5] riscv: Coding convention for xchg guoren
2020-11-24 13:43 ` [PATCH 2/5] riscv: Add QUEUED_SPINLOCKS & QUEUED_RWLOCKS supported guoren
2020-11-24 14:39 ` Peter Zijlstra
2020-11-24 15:00 ` Arnd Bergmann
2020-11-25 14:09 ` Guo Ren
2020-11-25 14:16 ` Peter Zijlstra
2020-11-25 14:31 ` Will Deacon
2020-11-26 1:36 ` Guo Ren
2020-11-26 8:53 ` Will Deacon
2020-11-25 0:52 ` Guo Ren [this message]
2020-11-25 14:18 ` Peter Zijlstra
2020-11-24 13:43 ` [PATCH 3/5] csky: Remove simple spinlock implementation guoren
2020-11-24 13:43 ` [PATCH 4/5] csky: Add QUEUED_SPINLOCKS supported guoren
2020-11-24 13:43 ` [PATCH 5/5] csky: Optimize atomic operations with correct barrier usage guoren
2020-11-24 14:29 ` [PATCH 1/5] riscv: Coding convention for xchg Peter Zijlstra
2020-11-25 14:18 ` Guo Ren
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