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diff for duplicates of <CAL_JsqJOxdE=gD4MyKuL5XZ57Z6UdM4_SU4qs26BNz6YcqM76A@mail.gmail.com>

diff --git a/a/1.txt b/N1/1.txt
index b2805fe..bf82463 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,6 +1,6 @@
 On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt <palmer@sifive.com> wrote:
 >
-> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh+dt at kernel.org wrote:
+> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh+dt@kernel.org wrote:
 > > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra <atish.patra@wdc.com> wrote:
 > >>
 > >> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.
@@ -92,4 +92,9 @@ like to get rid of /bindings/$arch/* except for maybe a few things.)
 
 > If everyone is OK with that then I vote we just go ahead and genericise the ARM
 > "cpu-map" stuff for CPU topology.  Sharing the implementation looks fairly
-> straight-forward as well.
\ No newline at end of file
+> straight-forward as well.
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index b2573e6..c672339 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -5,16 +5,29 @@
   "ref\0mhng-799bd6f4-e4af-481e-90d8-bdc0e30f2530\@palmer-si-x1c4\0"
 ]
 [
-  "From\0robh+dt\@kernel.org (Rob Herring)\0"
+  "From\0Rob Herring <robh+dt\@kernel.org>\0"
 ]
 [
-  "Subject\0[RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.\0"
+  "Subject\0Re: [RFC 1/2] dt-bindings: topology: Add RISC-V cpu topology.\0"
 ]
 [
   "Date\0Mon, 5 Nov 2018 14:10:36 -0600\0"
 ]
 [
-  "To\0linux-riscv\@lists.infradead.org\0"
+  "To\0Palmer Dabbelt <palmer\@sifive.com>\0"
+]
+[
+  "Cc\0Mark Rutland <mark.rutland\@arm.com>",
+  " devicetree\@vger.kernel.org",
+  " Damien.LeMoal\@wdc.com",
+  " alankao\@andestech.com",
+  " Zong Li <zong\@andestech.com>",
+  " Anup Patel <anup\@brainfault.org>",
+  " linux-kernel\@vger.kernel.org <linux-kernel\@vger.kernel.org>",
+  " Christoph Hellwig <hch\@infradead.org>",
+  " Atish Patra <atish.patra\@wdc.com>",
+  " linux-riscv\@lists.infradead.org",
+  " Thomas Gleixner <tglx\@linutronix.de>\0"
 ]
 [
   "\0000:1\0"
@@ -25,7 +38,7 @@
 [
   "On Mon, Nov 5, 2018 at 1:39 PM Palmer Dabbelt <palmer\@sifive.com> wrote:\n",
   ">\n",
-  "> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh+dt at kernel.org wrote:\n",
+  "> On Fri, 02 Nov 2018 06:09:39 PDT (-0700), robh+dt\@kernel.org wrote:\n",
   "> > On Thu, Nov 1, 2018 at 6:04 PM Atish Patra <atish.patra\@wdc.com> wrote:\n",
   "> >>\n",
   "> >> Define a RISC-V cpu topology. This is based on cpu-map in ARM world.\n",
@@ -117,7 +130,12 @@
   "\n",
   "> If everyone is OK with that then I vote we just go ahead and genericise the ARM\n",
   "> \"cpu-map\" stuff for CPU topology.  Sharing the implementation looks fairly\n",
-  "> straight-forward as well."
+  "> straight-forward as well.\n",
+  "\n",
+  "_______________________________________________\n",
+  "linux-riscv mailing list\n",
+  "linux-riscv\@lists.infradead.org\n",
+  "http://lists.infradead.org/mailman/listinfo/linux-riscv"
 ]
 
-58588e066c58609ec77f1cd3f832daec6c6faa6d85b94a4f287baf5fa462aae1
+83abf61ba9d34212bcf5f96ecf7758092c4e4330d7130b4e5de13c497697d9f0
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