Re: [PATCH] riscv: force hart_lottery to put in .sdata section

[Zong Li <zong.li@sifive.com>]

On Tue, Feb 4, 2020 at 7:40 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Feb 4, 2020 at 4:49 PM Zong Li <zong.li@sifive.com> wrote:
> >
> > In PIC code model, the zero initialized data always be put in .bss
> > section, so when building kernel as PIE, the hart_lottery won't present
> > in small data section, and it causes more than one harts to get the
> > lottery, because the main hart clears the content of .bss section
> > immediately after it getting the lottery.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >  arch/riscv/kernel/setup.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 22b671dbbcf1..45c63dc06360 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -40,7 +40,7 @@ struct screen_info screen_info = {
> >  #endif
> >
> >  /* The lucky hart to first increment this variable will boot the other cores */
> > -atomic_t hart_lottery;
> > +atomic_t hart_lottery __section(.sdata);
> >  unsigned long boot_cpu_hartid;
> >
> >  void __init parse_dtb(void)
> > --
> > 2.25.0
> >
> >
>
> Looks good to me. Please ensure that it is tested with both
> RV32 and RV64.
>

I had tested it on RV32 and RV64, it works on both.

> Reviewed-by: Anup Patel <anup@brainfault.org>
>
> Regards,
> Anup