* [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value
@ 2020-04-03 1:46 Atish Patra
2020-04-11 10:59 ` Marc Zyngier
0 siblings, 1 reply; 3+ messages in thread
From: Atish Patra @ 2020-04-03 1:46 UTC (permalink / raw)
To: linux-kernel
Cc: Jason Cooper, Marc Zyngier, Paul Walmsley, Atish Patra,
Palmer Dabbelt, Anup Patel, linux-riscv, Thomas Gleixner
As per the PLIC specification, maximum priority threshold value is 0x7
not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
there may be some implementation which checks the upper bound resulting in
an illegal access.
Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
interrupts upon cpu online/offline)
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
drivers/irqchip/irq-sifive-plic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index c34fb3ae0ff8..d0a71febdadc 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -56,7 +56,7 @@
#define CONTEXT_THRESHOLD 0x00
#define CONTEXT_CLAIM 0x04
-#define PLIC_DISABLE_THRESHOLD 0xf
+#define PLIC_DISABLE_THRESHOLD 0x7
#define PLIC_ENABLE_THRESHOLD 0
struct plic_priv {
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value
2020-04-03 1:46 [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value Atish Patra
@ 2020-04-11 10:59 ` Marc Zyngier
2020-04-13 7:16 ` Atish Patra
0 siblings, 1 reply; 3+ messages in thread
From: Marc Zyngier @ 2020-04-11 10:59 UTC (permalink / raw)
To: Atish Patra
Cc: Jason Cooper, Anup Patel, linux-kernel, Palmer Dabbelt,
Paul Walmsley, linux-riscv, Thomas Gleixner
On Thu, 2 Apr 2020 18:46:09 -0700
Atish Patra <atish.patra@wdc.com> wrote:
> As per the PLIC specification, maximum priority threshold value is 0x7
> not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
> there may be some implementation which checks the upper bound resulting in
> an illegal access.
>
> Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
> interrupts upon cpu online/offline)
Small nit: please write the "Fixes:" tag as documented in
process/submitting-patches.rst:
Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
(with quotes, and on a single line), as it otherwise breaks with the
lore-scrapping tooling which a bunch of us are now using.
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> drivers/irqchip/irq-sifive-plic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index c34fb3ae0ff8..d0a71febdadc 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -56,7 +56,7 @@
> #define CONTEXT_THRESHOLD 0x00
> #define CONTEXT_CLAIM 0x04
>
> -#define PLIC_DISABLE_THRESHOLD 0xf
> +#define PLIC_DISABLE_THRESHOLD 0x7
> #define PLIC_ENABLE_THRESHOLD 0
>
> struct plic_priv {
Queued for post -rc1.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value
2020-04-11 10:59 ` Marc Zyngier
@ 2020-04-13 7:16 ` Atish Patra
0 siblings, 0 replies; 3+ messages in thread
From: Atish Patra @ 2020-04-13 7:16 UTC (permalink / raw)
To: Marc Zyngier
Cc: Jason Cooper, Anup Patel, linux-kernel@vger.kernel.org List,
Atish Patra, Palmer Dabbelt, Paul Walmsley, linux-riscv,
Thomas Gleixner
On Sat, Apr 11, 2020 at 3:59 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Thu, 2 Apr 2020 18:46:09 -0700
> Atish Patra <atish.patra@wdc.com> wrote:
>
> > As per the PLIC specification, maximum priority threshold value is 0x7
> > not 0xF. Even though it doesn't cause any error in qemu/hifive unleashed,
> > there may be some implementation which checks the upper bound resulting in
> > an illegal access.
> >
> > Fixes: ccbe80bad571 (irqchip/sifive-plic: Enable/Disable external
> > interrupts upon cpu online/offline)
>
> Small nit: please write the "Fixes:" tag as documented in
> process/submitting-patches.rst:
>
> Fixes: ccbe80bad571 ("irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline")
>
> (with quotes, and on a single line), as it otherwise breaks with the
> lore-scrapping tooling which a bunch of us are now using.
>
Ahh Sorry for that. I will keep that in mind. I broke it into two
lines fearing a checkpatch warning.
But I guess I unleashed a bigger monster unknowingly ;)
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > drivers/irqchip/irq-sifive-plic.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index c34fb3ae0ff8..d0a71febdadc 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -56,7 +56,7 @@
> > #define CONTEXT_THRESHOLD 0x00
> > #define CONTEXT_CLAIM 0x04
> >
> > -#define PLIC_DISABLE_THRESHOLD 0xf
> > +#define PLIC_DISABLE_THRESHOLD 0x7
> > #define PLIC_ENABLE_THRESHOLD 0
> >
> > struct plic_priv {
>
> Queued for post -rc1.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-04-13 7:17 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-03 1:46 [PATCH] irqchip/sifive-plic: Fix maximum priority threshold value Atish Patra
2020-04-11 10:59 ` Marc Zyngier
2020-04-13 7:16 ` Atish Patra
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).