RE: [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs

[Yash Shah <yash.shah@sifive.com>]

> -----Original Message-----
> From: Dan Carpenter <dan.carpenter@oracle.com>
> Sent: 22 January 2020 15:07
> To: Yash Shah <yash.shah@sifive.com>
> Cc: linux-riscv@lists.infradead.org
> Subject: [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs
> 
> Hello Yash Shah,
> 
> The patch 96868dce644d: "gpio/sifive: Add GPIO driver for SiFive SoCs" from
> Dec 10, 2019, leads to the following static checker
> warning:
> 
> 	drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable()
> 	warn: passing casted pointer '&chip->irq_state' to 'assign_bit()' 32 vs
> 64.
> 
> drivers/gpio/gpio-sifive.c
>     86          gc->direction_input(gc, offset);
>     87
>     88          spin_lock_irqsave(&gc->bgpio_lock, flags);
>     89          /* Clear any sticky pending interrupts */
>     90          regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
>     91          regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
>     92          regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
>     93          regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
>     94          spin_unlock_irqrestore(&gc->bgpio_lock, flags);
>     95
>     96          /* Enable interrupts */
>     97          assign_bit(offset, (unsigned long *)&chip->irq_state, 1);
>                                                     ^^^^^^^^^^^^^^^^^ Better to just declare -
> >irq_state as an unsigned long so you don't have to worry about endianness.

Sure, will send the fix.
Thanks for reporting.

- Yash

> 
>     98          sifive_gpio_set_ie(chip, offset);
> 
> regards,
> dan carpenter