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* [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs
@ 2020-01-22  9:36 Dan Carpenter
  2020-01-24  4:44 ` Yash Shah
  0 siblings, 1 reply; 2+ messages in thread
From: Dan Carpenter @ 2020-01-22  9:36 UTC (permalink / raw)
  To: yash.shah; +Cc: linux-riscv

Hello Yash Shah,

The patch 96868dce644d: "gpio/sifive: Add GPIO driver for SiFive
SoCs" from Dec 10, 2019, leads to the following static checker
warning:

	drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable()
	warn: passing casted pointer '&chip->irq_state' to 'assign_bit()' 32 vs 64.

drivers/gpio/gpio-sifive.c
    86          gc->direction_input(gc, offset);
    87  
    88          spin_lock_irqsave(&gc->bgpio_lock, flags);
    89          /* Clear any sticky pending interrupts */
    90          regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
    91          regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
    92          regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
    93          regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
    94          spin_unlock_irqrestore(&gc->bgpio_lock, flags);
    95  
    96          /* Enable interrupts */
    97          assign_bit(offset, (unsigned long *)&chip->irq_state, 1);
                                                    ^^^^^^^^^^^^^^^^^
Better to just declare ->irq_state as an unsigned long so you don't
have to worry about endianness.

    98          sifive_gpio_set_ie(chip, offset);

regards,
dan carpenter


^ permalink raw reply	[flat|nested] 2+ messages in thread

* RE: [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs
  2020-01-22  9:36 [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs Dan Carpenter
@ 2020-01-24  4:44 ` Yash Shah
  0 siblings, 0 replies; 2+ messages in thread
From: Yash Shah @ 2020-01-24  4:44 UTC (permalink / raw)
  To: Dan Carpenter; +Cc: linux-riscv

> -----Original Message-----
> From: Dan Carpenter <dan.carpenter@oracle.com>
> Sent: 22 January 2020 15:07
> To: Yash Shah <yash.shah@sifive.com>
> Cc: linux-riscv@lists.infradead.org
> Subject: [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs
> 
> Hello Yash Shah,
> 
> The patch 96868dce644d: "gpio/sifive: Add GPIO driver for SiFive SoCs" from
> Dec 10, 2019, leads to the following static checker
> warning:
> 
> 	drivers/gpio/gpio-sifive.c:97 sifive_gpio_irq_enable()
> 	warn: passing casted pointer '&chip->irq_state' to 'assign_bit()' 32 vs
> 64.
> 
> drivers/gpio/gpio-sifive.c
>     86          gc->direction_input(gc, offset);
>     87
>     88          spin_lock_irqsave(&gc->bgpio_lock, flags);
>     89          /* Clear any sticky pending interrupts */
>     90          regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
>     91          regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
>     92          regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
>     93          regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
>     94          spin_unlock_irqrestore(&gc->bgpio_lock, flags);
>     95
>     96          /* Enable interrupts */
>     97          assign_bit(offset, (unsigned long *)&chip->irq_state, 1);
>                                                     ^^^^^^^^^^^^^^^^^ Better to just declare -
> >irq_state as an unsigned long so you don't have to worry about endianness.

Sure, will send the fix.
Thanks for reporting.

- Yash

> 
>     98          sifive_gpio_set_ie(chip, offset);
> 
> regards,
> dan carpenter


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2020-01-22  9:36 [bug report] gpio/sifive: Add GPIO driver for SiFive SoCs Dan Carpenter
2020-01-24  4:44 ` Yash Shah

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