* [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
@ 2024-05-07 10:45 Xiao Wang
2024-05-07 12:47 ` Pu Lehui
2024-05-10 20:56 ` Conor Dooley
0 siblings, 2 replies; 7+ messages in thread
From: Xiao Wang @ 2024-05-07 10:45 UTC (permalink / raw)
To: paul.walmsley, palmer, aou, luke.r.nels, xi.wang, bjorn
Cc: ast, daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, pulehui, haicheng.li, Xiao Wang
The Zba extension provides add.uw insn which can be used to implement
zext.w with rs2 set as ZERO.
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
arch/riscv/Kconfig | 19 +++++++++++++++++++
arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6bec1bce6586..0679127cc0ea 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
preemption. Enabling this config will result in higher memory
consumption due to the allocation of per-task's kernel Vector context.
+config TOOLCHAIN_HAS_ZBA
+ bool
+ default y
+ depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
+ depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
+ depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
+ depends on AS_HAS_OPTION_ARCH
+
config TOOLCHAIN_HAS_ZBB
bool
default y
@@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
depends on AS_HAS_OPTION_ARCH
+config RISCV_ISA_ZBA
+ bool "Zba extension support for bit manipulation instructions"
+ depends on TOOLCHAIN_HAS_ZBA
+ depends on RISCV_ALTERNATIVE
+ default y
+ help
+ Adds support to dynamically detect the presence of the ZBA
+ extension (address generation acceleration) and enable its usage.
+
+ If you don't know what to do here, say Y.
+
config RISCV_ISA_ZBB
bool "Zbb extension support for bit manipulation instructions"
depends on TOOLCHAIN_HAS_ZBB
diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index f4b6b3b9edda..18a7885ba95e 100644
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
return IS_ENABLED(CONFIG_RISCV_ISA_C);
}
+static inline bool rvzba_enabled(void)
+{
+ return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
+}
+
static inline bool rvzbb_enabled(void)
{
return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
@@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
return rv_css_insn(0x7, imm, rs2, 0x2);
}
+/* RV64-only ZBA instructions. */
+
+static inline u32 rvzba_zextw(u8 rd, u8 rs1)
+{
+ /* add.uw rd, rs1, ZERO */
+ return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
+}
+
#endif /* __riscv_xlen == 64 */
/* Helper functions that emit RVC instructions when possible. */
@@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
{
+ if (rvzba_enabled()) {
+ emit(rvzba_zextw(rd, rs), ctx);
+ return;
+ }
+
emit_slli(rd, rs, 32, ctx);
emit_srli(rd, rd, 32, ctx);
}
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-07 10:45 [PATCH] riscv, bpf: Optimize zextw insn with Zba extension Xiao Wang
@ 2024-05-07 12:47 ` Pu Lehui
2024-05-07 14:00 ` Ben Dooks
2024-05-08 11:20 ` Wang, Xiao W
2024-05-10 20:56 ` Conor Dooley
1 sibling, 2 replies; 7+ messages in thread
From: Pu Lehui @ 2024-05-07 12:47 UTC (permalink / raw)
To: Xiao Wang, paul.walmsley, palmer, aou, luke.r.nels, xi.wang, bjorn
Cc: ast, daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, haicheng.li
On 2024/5/7 18:45, Xiao Wang wrote:
> The Zba extension provides add.uw insn which can be used to implement
> zext.w with rs2 set as ZERO.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
> arch/riscv/Kconfig | 19 +++++++++++++++++++
> arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6bec1bce6586..0679127cc0ea 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> preemption. Enabling this config will result in higher memory
> consumption due to the allocation of per-task's kernel Vector context.
>
> +config TOOLCHAIN_HAS_ZBA
> + bool
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> + depends on AS_HAS_OPTION_ARCH
> +
> config TOOLCHAIN_HAS_ZBB
> bool
> default y
> @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> depends on AS_HAS_OPTION_ARCH
>
> +config RISCV_ISA_ZBA
> + bool "Zba extension support for bit manipulation instructions"
> + depends on TOOLCHAIN_HAS_ZBA
> + depends on RISCV_ALTERNATIVE
> + default y
> + help
> + Adds support to dynamically detect the presence of the ZBA
> + extension (address generation acceleration) and enable its usage.
It would be better to add Zba's function description like Zbb.
> +
> + If you don't know what to do here, say Y.
> +
> config RISCV_ISA_ZBB
> bool "Zbb extension support for bit manipulation instructions"
> depends on TOOLCHAIN_HAS_ZBB
> diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> index f4b6b3b9edda..18a7885ba95e 100644
> --- a/arch/riscv/net/bpf_jit.h
> +++ b/arch/riscv/net/bpf_jit.h
> @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
> return IS_ENABLED(CONFIG_RISCV_ISA_C);
> }
>
> +static inline bool rvzba_enabled(void)
> +{
> + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> +}
> +
> static inline bool rvzbb_enabled(void)
> {
> return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
> return rv_css_insn(0x7, imm, rs2, 0x2);
> }
>
> +/* RV64-only ZBA instructions. */
> +
> +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> +{
> + /* add.uw rd, rs1, ZERO */
> + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> +}
> +
> #endif /* __riscv_xlen == 64 */
>
> /* Helper functions that emit RVC instructions when possible. */
> @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
>
> static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
> {
> + if (rvzba_enabled()) {
> + emit(rvzba_zextw(rd, rs), ctx);
> + return;
> + }
Looks good to me. It seems that Zba has fewer uses in rv64 bpf jit.
> +
> emit_slli(rd, rs, 32, ctx);
> emit_srli(rd, rd, 32, ctx);
> }
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-07 12:47 ` Pu Lehui
@ 2024-05-07 14:00 ` Ben Dooks
2024-05-09 9:31 ` Wang, Xiao W
2024-05-08 11:20 ` Wang, Xiao W
1 sibling, 1 reply; 7+ messages in thread
From: Ben Dooks @ 2024-05-07 14:00 UTC (permalink / raw)
To: Pu Lehui, Xiao Wang, paul.walmsley, palmer, aou, luke.r.nels,
xi.wang, bjorn
Cc: ast, daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, haicheng.li
On 07/05/2024 13:47, Pu Lehui wrote:
>
> On 2024/5/7 18:45, Xiao Wang wrote:
>> The Zba extension provides add.uw insn which can be used to implement
>> zext.w with rs2 set as ZERO.
>>
>> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
>> ---
>> arch/riscv/Kconfig | 19 +++++++++++++++++++
>> arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
>> 2 files changed, 37 insertions(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 6bec1bce6586..0679127cc0ea 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
>> preemption. Enabling this config will result in higher memory
>> consumption due to the allocation of per-task's kernel Vector
>> context.
>> +config TOOLCHAIN_HAS_ZBA
>> + bool
>> + default y
>> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
>> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
>> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
>> + depends on AS_HAS_OPTION_ARCH
>> +
>> config TOOLCHAIN_HAS_ZBB
At this point would it be easier to ask the toolchain what's enabled
and put into kconfig via some sort of script?
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-07 12:47 ` Pu Lehui
2024-05-07 14:00 ` Ben Dooks
@ 2024-05-08 11:20 ` Wang, Xiao W
1 sibling, 0 replies; 7+ messages in thread
From: Wang, Xiao W @ 2024-05-08 11:20 UTC (permalink / raw)
To: Pu Lehui, paul.walmsley, palmer, aou, luke.r.nels, xi.wang, bjorn
Cc: ast, daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, Li, Haicheng
> -----Original Message-----
> From: Pu Lehui <pulehui@huawei.com>
> Sent: Tuesday, May 7, 2024 8:47 PM
> To: Wang, Xiao W <xiao.w.wang@intel.com>; paul.walmsley@sifive.com;
> palmer@dabbelt.com; aou@eecs.berkeley.edu; luke.r.nels@gmail.com;
> xi.wang@gmail.com; bjorn@kernel.org
> Cc: ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
>
>
> On 2024/5/7 18:45, Xiao Wang wrote:
> > The Zba extension provides add.uw insn which can be used to implement
> > zext.w with rs2 set as ZERO.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> > ---
> > arch/riscv/Kconfig | 19 +++++++++++++++++++
> > arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> > 2 files changed, 37 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 6bec1bce6586..0679127cc0ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> > preemption. Enabling this config will result in higher memory
> > consumption due to the allocation of per-task's kernel Vector
> context.
> >
> > +config TOOLCHAIN_HAS_ZBA
> > + bool
> > + default y
> > + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> > + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> > + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> > + depends on AS_HAS_OPTION_ARCH
> > +
> > config TOOLCHAIN_HAS_ZBB
> > bool
> > default y
> > @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> > def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> > depends on AS_HAS_OPTION_ARCH
> >
> > +config RISCV_ISA_ZBA
> > + bool "Zba extension support for bit manipulation instructions"
> > + depends on TOOLCHAIN_HAS_ZBA
> > + depends on RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Adds support to dynamically detect the presence of the ZBA
> > + extension (address generation acceleration) and enable its usage.
>
> It would be better to add Zba's function description like Zbb.
OK, would add some description on next version.
Thanks,
Xiao
>
> > +
> > + If you don't know what to do here, say Y.
> > +
> > config RISCV_ISA_ZBB
> > bool "Zbb extension support for bit manipulation instructions"
> > depends on TOOLCHAIN_HAS_ZBB
> > diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
> > index f4b6b3b9edda..18a7885ba95e 100644
> > --- a/arch/riscv/net/bpf_jit.h
> > +++ b/arch/riscv/net/bpf_jit.h
> > @@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
> > return IS_ENABLED(CONFIG_RISCV_ISA_C);
> > }
> >
> > +static inline bool rvzba_enabled(void)
> > +{
> > + return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
> > +}
> > +
> > static inline bool rvzbb_enabled(void)
> > {
> > return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
> riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
> > @@ -937,6 +942,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
> > return rv_css_insn(0x7, imm, rs2, 0x2);
> > }
> >
> > +/* RV64-only ZBA instructions. */
> > +
> > +static inline u32 rvzba_zextw(u8 rd, u8 rs1)
> > +{
> > + /* add.uw rd, rs1, ZERO */
> > + return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
> > +}
> > +
> > #endif /* __riscv_xlen == 64 */
> >
> > /* Helper functions that emit RVC instructions when possible. */
> > @@ -1159,6 +1172,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct
> rv_jit_context *ctx)
> >
> > static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
> > {
> > + if (rvzba_enabled()) {
> > + emit(rvzba_zextw(rd, rs), ctx);
> > + return;
> > + }
>
> Looks good to me. It seems that Zba has fewer uses in rv64 bpf jit.
>
> > +
> > emit_slli(rd, rs, 32, ctx);
> > emit_srli(rd, rd, 32, ctx);
> > }
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-07 14:00 ` Ben Dooks
@ 2024-05-09 9:31 ` Wang, Xiao W
0 siblings, 0 replies; 7+ messages in thread
From: Wang, Xiao W @ 2024-05-09 9:31 UTC (permalink / raw)
To: ben.dooks, Pu Lehui, paul.walmsley, palmer, aou, luke.r.nels,
xi.wang, bjorn
Cc: ast, daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, Li, Haicheng
Hi Ben,
> -----Original Message-----
> From: ben.dooks@codethink.co.uk <ben.dooks@codethink.co.uk>
> Sent: Tuesday, May 7, 2024 10:00 PM
> To: Pu Lehui <pulehui@huawei.com>; Wang, Xiao W
> <xiao.w.wang@intel.com>; paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> bjorn@kernel.org
> Cc: ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
>
> On 07/05/2024 13:47, Pu Lehui wrote:
> >
> > On 2024/5/7 18:45, Xiao Wang wrote:
> >> The Zba extension provides add.uw insn which can be used to implement
> >> zext.w with rs2 set as ZERO.
> >>
> >> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> >> ---
> >> arch/riscv/Kconfig | 19 +++++++++++++++++++
> >> arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> >> 2 files changed, 37 insertions(+)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index 6bec1bce6586..0679127cc0ea 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> >> preemption. Enabling this config will result in higher memory
> >> consumption due to the allocation of per-task's kernel Vector
> >> context.
> >> +config TOOLCHAIN_HAS_ZBA
> >> + bool
> >> + default y
> >> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> >> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> >> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> >> + depends on AS_HAS_OPTION_ARCH
> >> +
> >> config TOOLCHAIN_HAS_ZBB
>
> At this point would it be easier to ask the toolchain what's enabled
> and put into kconfig via some sort of script?
You mean to use some sort of script to automatically detect whether LD linker
can support a certain riscv extension?
I just went through the help guide of riscv64-linux-gnu-ld, and did some trial,
the "--architecture" argument usage is different from the CC's "-march". I can't find
other relevant args. It looks currently there's no direct method to dump the
supported riscv extensions of a LD.
Then I tried below test to see if we can check it via building from /dev/null, just like
the cc-option does.
Note: here CC is Zbb capable
CC -march=rv64gc_zbb -x c -c /dev/null -o tmp.o && LD tmp.o -o tmp.elf
I find that whether LD is Zbb capable or not, the above command just outputs
"warning: cannot find entry symbol _start ..", no error comes with older LD.
When we provide some Zbb-arch-tagged non-empty *.o file to the LD, then
the older LD would error out "unsupported ISA subset ..".
But I'm afraid it's not a good idea to add a source file for each extension detection.
Maybe in future there would be an easy way to ask the LD what riscv extensions
are supported.
BRs,
Xiao
>
> --
> Ben Dooks http://www.codethink.co.uk/
> Senior Engineer Codethink - Providing Genius
>
> https://www.codethink.co.uk/privacy.html
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-07 10:45 [PATCH] riscv, bpf: Optimize zextw insn with Zba extension Xiao Wang
2024-05-07 12:47 ` Pu Lehui
@ 2024-05-10 20:56 ` Conor Dooley
2024-05-11 1:17 ` Wang, Xiao W
1 sibling, 1 reply; 7+ messages in thread
From: Conor Dooley @ 2024-05-10 20:56 UTC (permalink / raw)
To: Xiao Wang
Cc: paul.walmsley, palmer, aou, luke.r.nels, xi.wang, bjorn, ast,
daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, pulehui, haicheng.li
[-- Attachment #1.1: Type: text/plain, Size: 2035 bytes --]
On Tue, May 07, 2024 at 06:45:28PM +0800, Xiao Wang wrote:
> The Zba extension provides add.uw insn which can be used to implement
> zext.w with rs2 set as ZERO.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
> arch/riscv/Kconfig | 19 +++++++++++++++++++
> arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6bec1bce6586..0679127cc0ea 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> preemption. Enabling this config will result in higher memory
> consumption due to the allocation of per-task's kernel Vector context.
>
> +config TOOLCHAIN_HAS_ZBA
> + bool
> + default y
> + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> + depends on AS_HAS_OPTION_ARCH
> +
> config TOOLCHAIN_HAS_ZBB
> bool
> default y
> @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> depends on AS_HAS_OPTION_ARCH
>
> +config RISCV_ISA_ZBA
> + bool "Zba extension support for bit manipulation instructions"
> + depends on TOOLCHAIN_HAS_ZBA
> + depends on RISCV_ALTERNATIVE
> + default y
> + help
> + Adds support to dynamically detect the presence of the ZBA
> + extension (address generation acceleration) and enable its usage.
Recently I sent some patches to reword other extensions' help text,
because the "add support to dynamically detect" had confused people a
bit. Dynamic detection is done regardless of config options for Zba.
The wording I went with in my patch for Zbb was:
Add support for enabling optimisations in the kernel when the
Zbb extension is detected at boot.
Could you use something similar here in the opening sentence please?
Thanks,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
2024-05-10 20:56 ` Conor Dooley
@ 2024-05-11 1:17 ` Wang, Xiao W
0 siblings, 0 replies; 7+ messages in thread
From: Wang, Xiao W @ 2024-05-11 1:17 UTC (permalink / raw)
To: Conor Dooley
Cc: paul.walmsley, palmer, aou, luke.r.nels, xi.wang, bjorn, ast,
daniel, andrii, martin.lau, eddyz87, song, yonghong.song,
john.fastabend, kpsingh, sdf, haoluo, jolsa, linux-riscv,
linux-kernel, bpf, pulehui, Li, Haicheng
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Saturday, May 11, 2024 4:56 AM
> To: Wang, Xiao W <xiao.w.wang@intel.com>
> Cc: paul.walmsley@sifive.com; palmer@dabbelt.com;
> aou@eecs.berkeley.edu; luke.r.nels@gmail.com; xi.wang@gmail.com;
> bjorn@kernel.org; ast@kernel.org; daniel@iogearbox.net; andrii@kernel.org;
> martin.lau@linux.dev; eddyz87@gmail.com; song@kernel.org;
> yonghong.song@linux.dev; john.fastabend@gmail.com; kpsingh@kernel.org;
> sdf@google.com; haoluo@google.com; jolsa@kernel.org; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org; bpf@vger.kernel.org;
> pulehui@huawei.com; Li, Haicheng <haicheng.li@intel.com>
> Subject: Re: [PATCH] riscv, bpf: Optimize zextw insn with Zba extension
>
> On Tue, May 07, 2024 at 06:45:28PM +0800, Xiao Wang wrote:
> > The Zba extension provides add.uw insn which can be used to implement
> > zext.w with rs2 set as ZERO.
> >
> > Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> > ---
> > arch/riscv/Kconfig | 19 +++++++++++++++++++
> > arch/riscv/net/bpf_jit.h | 18 ++++++++++++++++++
> > 2 files changed, 37 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 6bec1bce6586..0679127cc0ea 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -586,6 +586,14 @@ config RISCV_ISA_V_PREEMPTIVE
> > preemption. Enabling this config will result in higher memory
> > consumption due to the allocation of per-task's kernel Vector
> context.
> >
> > +config TOOLCHAIN_HAS_ZBA
> > + bool
> > + default y
> > + depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64ima_zba)
> > + depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32ima_zba)
> > + depends on LLD_VERSION >= 150000 || LD_VERSION >= 23900
> > + depends on AS_HAS_OPTION_ARCH
> > +
> > config TOOLCHAIN_HAS_ZBB
> > bool
> > default y
> > @@ -601,6 +609,17 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
> > def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
> > depends on AS_HAS_OPTION_ARCH
> >
> > +config RISCV_ISA_ZBA
> > + bool "Zba extension support for bit manipulation instructions"
> > + depends on TOOLCHAIN_HAS_ZBA
> > + depends on RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Adds support to dynamically detect the presence of the ZBA
> > + extension (address generation acceleration) and enable its usage.
>
> Recently I sent some patches to reword other extensions' help text,
> because the "add support to dynamically detect" had confused people a
> bit. Dynamic detection is done regardless of config options for Zba.
> The wording I went with in my patch for Zbb was:
> Add support for enabling optimisations in the kernel when the
> Zbb extension is detected at boot.
> Could you use something similar here in the opening sentence please?
Agree with you. Yes, I would reword it in next version.
Thanks,
Xiao
>
> Thanks,
> Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2024-05-11 1:17 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-07 10:45 [PATCH] riscv, bpf: Optimize zextw insn with Zba extension Xiao Wang
2024-05-07 12:47 ` Pu Lehui
2024-05-07 14:00 ` Ben Dooks
2024-05-09 9:31 ` Wang, Xiao W
2024-05-08 11:20 ` Wang, Xiao W
2024-05-10 20:56 ` Conor Dooley
2024-05-11 1:17 ` Wang, Xiao W
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).