* [RFC PATCH 1/4] riscv: Optimize satp_mode data type
2022-07-05 10:05 [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support guoren
@ 2022-07-05 10:05 ` guoren
2022-07-05 17:26 ` Christoph Hellwig
2022-07-05 10:05 ` [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile guoren
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: guoren @ 2022-07-05 10:05 UTC (permalink / raw)
To: palmer; +Cc: linux-riscv, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Fixup satp_mode data type. Use ulong instead of u64 for rv32
compatibility. Because the u64 type didn't cause any real problem, make
it as optimized.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/pgtable.h | 2 +-
arch/riscv/mm/init.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 1d1be9d9419c..edc68759b69d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -833,7 +833,7 @@ extern uintptr_t _dtb_early_pa;
#define dtb_early_va _dtb_early_va
#define dtb_early_pa _dtb_early_pa
#endif /* CONFIG_XIP_KERNEL */
-extern u64 satp_mode;
+extern ulong satp_mode;
extern bool pgtable_l4_enabled;
void paging_init(void);
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index d466ec670e1f..eea147b1a617 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -38,9 +38,9 @@ EXPORT_SYMBOL(kernel_map);
#endif
#ifdef CONFIG_64BIT
-u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
+ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
#else
-u64 satp_mode __ro_after_init = SATP_MODE_32;
+ulong satp_mode __ro_after_init = SATP_MODE_32;
#endif
EXPORT_SYMBOL(satp_mode);
--
2.36.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 1/4] riscv: Optimize satp_mode data type
2022-07-05 10:05 ` [RFC PATCH 1/4] riscv: Optimize satp_mode data type guoren
@ 2022-07-05 17:26 ` Christoph Hellwig
2022-07-05 23:45 ` Guo Ren
0 siblings, 1 reply; 14+ messages in thread
From: Christoph Hellwig @ 2022-07-05 17:26 UTC (permalink / raw)
To: guoren; +Cc: palmer, linux-riscv, Guo Ren
On Tue, Jul 05, 2022 at 06:05:20AM -0400, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Fixup satp_mode data type. Use ulong instead of u64 for rv32
> compatibility. Because the u64 type didn't cause any real problem, make
> it as optimized.
The changelog loooks odd, but given that CSR are Xlen sized this
is the right thing to do even without further justification.
> -extern u64 satp_mode;
> +extern ulong satp_mode;
.. but please spell out unsigned long.
> #ifdef CONFIG_64BIT
> -u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
> +ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
> #else
> -u64 satp_mode __ro_after_init = SATP_MODE_32;
> +ulong satp_mode __ro_after_init = SATP_MODE_32;
> #endif
And maybe make this less of a mess while we're at it:
#ifdef CONFIG_32BIT
#define SATP_DEFAULT SATP_MODE_32
#elif defined(CONFIG_XIP_KERNEL)
#define SATP_DEFAULT SATP_MODE_39
#else
#define SATP_DEFAULT SATP_MODE_57
#endif
unsigned long satp_mode __ro_after_init = SATP_DEFAULT;
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 1/4] riscv: Optimize satp_mode data type
2022-07-05 17:26 ` Christoph Hellwig
@ 2022-07-05 23:45 ` Guo Ren
0 siblings, 0 replies; 14+ messages in thread
From: Guo Ren @ 2022-07-05 23:45 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: Palmer Dabbelt, linux-riscv, Guo Ren
On Wed, Jul 6, 2022 at 1:26 AM Christoph Hellwig <hch@infradead.org> wrote:
>
> On Tue, Jul 05, 2022 at 06:05:20AM -0400, guoren@kernel.org wrote:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Fixup satp_mode data type. Use ulong instead of u64 for rv32
> > compatibility. Because the u64 type didn't cause any real problem, make
> > it as optimized.
>
> The changelog loooks odd, but given that CSR are Xlen sized this
> is the right thing to do even without further justification.
The last sentence is the reason not to add Fixes: tag.
>
> > -extern u64 satp_mode;
> > +extern ulong satp_mode;
>
> .. but please spell out unsigned long.
>
> > #ifdef CONFIG_64BIT
> > -u64 satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
> > +ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ? SATP_MODE_57 : SATP_MODE_39;
> > #else
> > -u64 satp_mode __ro_after_init = SATP_MODE_32;
> > +ulong satp_mode __ro_after_init = SATP_MODE_32;
> > #endif
>
> And maybe make this less of a mess while we're at it:
>
> #ifdef CONFIG_32BIT
> #define SATP_DEFAULT SATP_MODE_32
> #elif defined(CONFIG_XIP_KERNEL)
> #define SATP_DEFAULT SATP_MODE_39
> #else
> #define SATP_DEFAULT SATP_MODE_57
> #endif
>
> unsigned long satp_mode __ro_after_init = SATP_DEFAULT;
It a little involves the other coding convention work.
ulong satp_mode __ro_after_init = !IS_ENABLED(CONFIG_XIP_KERNEL) ?
SATP_MODE_57 : SATP_MODE_39;B
The above seems readable & clear to me.
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile
2022-07-05 10:05 [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support guoren
2022-07-05 10:05 ` [RFC PATCH 1/4] riscv: Optimize satp_mode data type guoren
@ 2022-07-05 10:05 ` guoren
2022-07-08 8:50 ` Heiko Stübner
2022-07-05 10:05 ` [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h guoren
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: guoren @ 2022-07-05 10:05 UTC (permalink / raw)
To: palmer; +Cc: linux-riscv, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Make compile cleaner and don't reference the THEAD_PBMT data struct when
CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to
support rv32.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/errata_list.h | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 416ead0f9a65..47175d91773d 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
* in the default case.
*/
#define ALT_SVPBMT_SHIFT 61
+
+#ifdef CONFIG_ERRATA_THEAD_PBMT
#define ALT_THEAD_PBMT_SHIFT 59
#define ALT_SVPBMT(_val, prot) \
asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
@@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
"I"(ALT_SVPBMT_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT))
-#ifdef CONFIG_ERRATA_THEAD_PBMT
/*
* IO/NOCACHE memory types are handled together with svpbmt,
* so on T-Head chips, check if no other memory type is set,
@@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \
"I"(ALT_THEAD_PBMT_SHIFT) \
: "t3")
#else
+#define ALT_SVPBMT(_val, prot) \
+asm(ALTERNATIVE("li %0, 0\t\nnop", \
+ "li %0, %1\t\nslli %0,%0,%2", 0, \
+ CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \
+ : "=r"(_val) \
+ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
+ "I"(ALT_SVPBMT_SHIFT))
+
#define ALT_THEAD_PMA(_val)
#endif
--
2.36.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile
2022-07-05 10:05 ` [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile guoren
@ 2022-07-08 8:50 ` Heiko Stübner
2022-07-09 16:24 ` Guo Ren
2022-07-10 2:25 ` Guo Ren
0 siblings, 2 replies; 14+ messages in thread
From: Heiko Stübner @ 2022-07-08 8:50 UTC (permalink / raw)
To: palmer, linux-riscv; +Cc: linux-riscv, Guo Ren, Guo Ren, guoren
Hi Guo,
Am Dienstag, 5. Juli 2022, 12:05:21 CEST schrieb guoren@kernel.org:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Make compile cleaner and don't reference the THEAD_PBMT data struct when
> CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to
> support rv32.
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/include/asm/errata_list.h | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 416ead0f9a65..47175d91773d 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
> * in the default case.
> */
> #define ALT_SVPBMT_SHIFT 61
> +
> +#ifdef CONFIG_ERRATA_THEAD_PBMT
I don't really think that is necessary and actually makes the code
more complex than needed.
Each alternative-entry already has the dependency on
CONFIG_* ... i.e. CONFIG_RISCV_ISA_SVPBMT and CONFIG_ERRATA_THEAD_PBMT
When you look at alternative-macros.h you'll see this translating to the
enable argument in ALT_NEW_CONTENT.
So only when that is active is the alternative section added to the build.
I.e. that translates to:
.if IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)
.pushsection .alternative, "a"
...
So when CONFIG_ERRATA_THEAD_PBMT is disabled the whole alternative
part never gets added already, so there shouldn't be any need to make the
source more complicated.
Heiko
> #define ALT_THEAD_PBMT_SHIFT 59
> #define ALT_SVPBMT(_val, prot) \
> asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> @@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> "I"(ALT_SVPBMT_SHIFT), \
> "I"(ALT_THEAD_PBMT_SHIFT))
>
> -#ifdef CONFIG_ERRATA_THEAD_PBMT
> /*
> * IO/NOCACHE memory types are handled together with svpbmt,
> * so on T-Head chips, check if no other memory type is set,
> @@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \
> "I"(ALT_THEAD_PBMT_SHIFT) \
> : "t3")
> #else
> +#define ALT_SVPBMT(_val, prot) \
> +asm(ALTERNATIVE("li %0, 0\t\nnop", \
> + "li %0, %1\t\nslli %0,%0,%2", 0, \
> + CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \
> + : "=r"(_val) \
> + : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
> + "I"(ALT_SVPBMT_SHIFT))
> +
> #define ALT_THEAD_PMA(_val)
> #endif
>
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile
2022-07-08 8:50 ` Heiko Stübner
@ 2022-07-09 16:24 ` Guo Ren
2022-07-10 2:25 ` Guo Ren
1 sibling, 0 replies; 14+ messages in thread
From: Guo Ren @ 2022-07-09 16:24 UTC (permalink / raw)
To: Heiko Stübner; +Cc: Palmer Dabbelt, linux-riscv, Guo Ren
On Fri, Jul 8, 2022 at 4:51 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Guo,
>
> Am Dienstag, 5. Juli 2022, 12:05:21 CEST schrieb guoren@kernel.org:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Make compile cleaner and don't reference the THEAD_PBMT data struct when
> > CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to
> > support rv32.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/errata_list.h | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 416ead0f9a65..47175d91773d 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
> > * in the default case.
> > */
> > #define ALT_SVPBMT_SHIFT 61
> > +
> > +#ifdef CONFIG_ERRATA_THEAD_PBMT
>
> I don't really think that is necessary and actually makes the code
> more complex than needed.
>
> Each alternative-entry already has the dependency on
> CONFIG_* ... i.e. CONFIG_RISCV_ISA_SVPBMT and CONFIG_ERRATA_THEAD_PBMT
>
> When you look at alternative-macros.h you'll see this translating to the
> enable argument in ALT_NEW_CONTENT.
>
> So only when that is active is the alternative section added to the build.
> I.e. that translates to:
>
> .if IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)
> .pushsection .alternative, "a"
> ...
>
> So when CONFIG_ERRATA_THEAD_PBMT is disabled the whole alternative
> part never gets added already, so there shouldn't be any need to make the
> source more complicated.
No, we need this for rv32 compile.
➜ linux git:(rv32svpbmt_v2_tmp) make ARCH=riscv
CROSS_COMPILE=riscv32-buildroot-linux-gnu- EXTRA_CFLAGS+=-g
O=../build-rv32/ -skj all
In file included from
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable.h:15,
from
/home/guoren/source/kernel/linux/include/linux/pgtable.h:6,
from /home/guoren/source/kernel/linux/include/linux/mm.h:29,
from
/home/guoren/source/kernel/linux/arch/riscv/kernel/asm-offsets.c:10:
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:50:
warning: "ALT_SVPBMT_SHIFT" redefined
50 | #define ALT_SVPBMT_SHIFT (__riscv_xlen-3)
|
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:49:
note: this is the location of the previous definition
49 | #define ALT_SVPBMT_SHIFT 61
|
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:
In function ‘riscv_page_mtmask’:
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:43:18:
error: ‘_PAGE_MTMASK_THEAD’ undeclared (first use in this function)
43 | ALT_SVPBMT(val, _PAGE_MTMASK);
| ^~~~~~~~~~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:61:9:
note: in definition of macro ‘ALT_SVPBMT’
61 | "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
| ^~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:43:18:
note: each undeclared identifier is reported only once for each
function it appears in
43 | ALT_SVPBMT(val, _PAGE_MTMASK);
| ^~~~~~~~~~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:61:9:
note: in definition of macro ‘ALT_SVPBMT’
61 | "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
| ^~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:
In function ‘riscv_page_nocache’:
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:51:18:
error: ‘_PAGE_NOCACHE_THEAD’ undeclared (first use in this function)
51 | ALT_SVPBMT(val, _PAGE_NOCACHE);
| ^~~~~~~~~~~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:61:9:
note: in definition of macro ‘ALT_SVPBMT’
61 | "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
| ^~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:
In function ‘riscv_page_io’:
/home/guoren/source/kernel/linux/arch/riscv/include/asm/pgtable-bits.h:59:18:
error: ‘_PAGE_IO_THEAD’ undeclared (first use in this function)
59 | ALT_SVPBMT(val, _PAGE_IO);
| ^~~~~~~~
/home/guoren/source/kernel/linux/arch/riscv/include/asm/errata_list.h:61:9:
note: in definition of macro ‘ALT_SVPBMT’
61 | "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
| ^~~~
make[2]: *** [/home/guoren/source/kernel/linux/scripts/Makefile.build:117:
arch/riscv/kernel/asm-offsets.s] Error 1
make[2]: Target '__build' not remade because of errors.
make[1]: *** [/home/guoren/source/kernel/linux/Makefile:1200: prepare0] Error 2
make[1]: Target 'all' not remade because of errors.
make: *** [Makefile:219: __sub-make] Error 2
make: Target 'all' not remade because of errors.
>
>
> Heiko
>
> > #define ALT_THEAD_PBMT_SHIFT 59
> > #define ALT_SVPBMT(_val, prot) \
> > asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> > @@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> > "I"(ALT_SVPBMT_SHIFT), \
> > "I"(ALT_THEAD_PBMT_SHIFT))
> >
> > -#ifdef CONFIG_ERRATA_THEAD_PBMT
> > /*
> > * IO/NOCACHE memory types are handled together with svpbmt,
> > * so on T-Head chips, check if no other memory type is set,
> > @@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \
> > "I"(ALT_THEAD_PBMT_SHIFT) \
> > : "t3")
> > #else
> > +#define ALT_SVPBMT(_val, prot) \
> > +asm(ALTERNATIVE("li %0, 0\t\nnop", \
> > + "li %0, %1\t\nslli %0,%0,%2", 0, \
> > + CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \
> > + : "=r"(_val) \
> > + : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
> > + "I"(ALT_SVPBMT_SHIFT))
> > +
> > #define ALT_THEAD_PMA(_val)
> > #endif
> >
> >
>
>
>
>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile
2022-07-08 8:50 ` Heiko Stübner
2022-07-09 16:24 ` Guo Ren
@ 2022-07-10 2:25 ` Guo Ren
1 sibling, 0 replies; 14+ messages in thread
From: Guo Ren @ 2022-07-10 2:25 UTC (permalink / raw)
To: Heiko Stübner; +Cc: Palmer Dabbelt, linux-riscv, Guo Ren
On Fri, Jul 8, 2022 at 4:51 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Guo,
>
> Am Dienstag, 5. Juli 2022, 12:05:21 CEST schrieb guoren@kernel.org:
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > Make compile cleaner and don't reference the THEAD_PBMT data struct when
> > CONFIG_ERRATA_THEAD_PBMT=y. Next, we could cleanly make svpbmt to
> > support rv32.
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/errata_list.h | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index 416ead0f9a65..47175d91773d 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -47,6 +47,8 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
> > * in the default case.
> > */
> > #define ALT_SVPBMT_SHIFT 61
> > +
> > +#ifdef CONFIG_ERRATA_THEAD_PBMT
>
> I don't really think that is necessary and actually makes the code
> more complex than needed.
>
> Each alternative-entry already has the dependency on
> CONFIG_* ... i.e. CONFIG_RISCV_ISA_SVPBMT and CONFIG_ERRATA_THEAD_PBMT
>
> When you look at alternative-macros.h you'll see this translating to the
> enable argument in ALT_NEW_CONTENT.
>
> So only when that is active is the alternative section added to the build.
> I.e. that translates to:
>
> .if IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)
> .pushsection .alternative, "a"
> ...
Above can't affect the below:
: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
"I"(ALT_SVPBMT_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT))
So CONFIG_ERRATA_THEAD_PBMT is not clean as you think, compiler still
process the "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT)" &
"I"(ALT_THEAD_PBMT_SHIFT).
>
> So when CONFIG_ERRATA_THEAD_PBMT is disabled the whole alternative
> part never gets added already, so there shouldn't be any need to make the
> source more complicated.
>
>
> Heiko
>
> > #define ALT_THEAD_PBMT_SHIFT 59
> > #define ALT_SVPBMT(_val, prot) \
> > asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> > @@ -60,7 +62,6 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
> > "I"(ALT_SVPBMT_SHIFT), \
> > "I"(ALT_THEAD_PBMT_SHIFT))
> >
> > -#ifdef CONFIG_ERRATA_THEAD_PBMT
> > /*
> > * IO/NOCACHE memory types are handled together with svpbmt,
> > * so on T-Head chips, check if no other memory type is set,
> > @@ -90,6 +91,14 @@ asm volatile(ALTERNATIVE( \
> > "I"(ALT_THEAD_PBMT_SHIFT) \
> > : "t3")
> > #else
> > +#define ALT_SVPBMT(_val, prot) \
> > +asm(ALTERNATIVE("li %0, 0\t\nnop", \
> > + "li %0, %1\t\nslli %0,%0,%2", 0, \
> > + CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT) \
> > + : "=r"(_val) \
> > + : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
> > + "I"(ALT_SVPBMT_SHIFT))
> > +
> > #define ALT_THEAD_PMA(_val)
> > #endif
> >
> >
>
>
>
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h
2022-07-05 10:05 [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support guoren
2022-07-05 10:05 ` [RFC PATCH 1/4] riscv: Optimize satp_mode data type guoren
2022-07-05 10:05 ` [RFC PATCH 2/4] riscv: Cleanup ERRATA_THEAD_PBMT for rv32 svpbmt compile guoren
@ 2022-07-05 10:05 ` guoren
2022-07-08 6:10 ` Guo Ren
2022-07-05 10:05 ` [RFC PATCH 4/4] riscv: Change rv32p34 to rv32p31 for svpbmt guoren
2022-07-05 17:22 ` [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support Christoph Hellwig
4 siblings, 1 reply; 14+ messages in thread
From: guoren @ 2022-07-05 10:05 UTC (permalink / raw)
To: palmer; +Cc: linux-riscv, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
This patch is preparation for rv32 svpbmt, which only moves the svpbmt
bits definitions into the standard header and no other functionality
modification. Here is the list of modification:
- Change u64 to ulong of riscv_page_nocache/mtmask/io functions
- Using __riscv_xlen instead of 64
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/include/asm/pgtable-32.h | 16 --------
arch/riscv/include/asm/pgtable-64.h | 55 ---------------------------
arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++
arch/riscv/include/asm/pgtable.h | 5 +++
4 files changed, 58 insertions(+), 71 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 59ba1fbaf784..63b023bd4845 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -7,8 +7,6 @@
#define _ASM_RISCV_PGTABLE_32_H
#include <asm-generic/pgtable-nopmd.h>
-#include <linux/bits.h>
-#include <linux/const.h>
/* Size of region mapped by a page global directory */
#define PGDIR_SHIFT 22
@@ -17,20 +15,6 @@
#define MAX_POSSIBLE_PHYSMEM_BITS 34
-/*
- * rv32 PTE format:
- * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * PFN reserved for SW D A G U X W R V
- */
#define _PAGE_PFN_MASK GENMASK(31, 10)
-#define _PAGE_NOCACHE 0
-#define _PAGE_IO 0
-#define _PAGE_MTMASK 0
-
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
- _PAGE_WRITE | _PAGE_EXEC | \
- _PAGE_USER | _PAGE_GLOBAL))
-
#endif /* _ASM_RISCV_PGTABLE_32_H */
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 5c2aba5efbd0..3263b910e7d2 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -6,10 +6,6 @@
#ifndef _ASM_RISCV_PGTABLE_64_H
#define _ASM_RISCV_PGTABLE_64_H
-#include <linux/bits.h>
-#include <linux/const.h>
-#include <asm/errata_list.h>
-
extern bool pgtable_l4_enabled;
extern bool pgtable_l5_enabled;
@@ -67,25 +63,8 @@ typedef struct {
#define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
-/*
- * rv64 PTE format:
- * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- * N MT RSV PFN reserved for SW D A G U X W R V
- */
#define _PAGE_PFN_MASK GENMASK(53, 10)
-/*
- * [62:61] Svpbmt Memory Type definitions:
- *
- * 00 - PMA Normal Cacheable, No change to implied PMA memory type
- * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
- * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
- * 11 - Rsvd Reserved for future standard use
- */
-#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
-#define _PAGE_IO_SVPBMT (1UL << 62)
-#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
-
/*
* [63:59] T-Head Memory Type definitions:
*
@@ -98,40 +77,6 @@ typedef struct {
#define _PAGE_IO_THEAD (1UL << 63)
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
-static inline u64 riscv_page_mtmask(void)
-{
- u64 val;
-
- ALT_SVPBMT(val, _PAGE_MTMASK);
- return val;
-}
-
-static inline u64 riscv_page_nocache(void)
-{
- u64 val;
-
- ALT_SVPBMT(val, _PAGE_NOCACHE);
- return val;
-}
-
-static inline u64 riscv_page_io(void)
-{
- u64 val;
-
- ALT_SVPBMT(val, _PAGE_IO);
- return val;
-}
-
-#define _PAGE_NOCACHE riscv_page_nocache()
-#define _PAGE_IO riscv_page_io()
-#define _PAGE_MTMASK riscv_page_mtmask()
-
-/* Set of bits to preserve across pte_modify() */
-#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
- _PAGE_WRITE | _PAGE_EXEC | \
- _PAGE_USER | _PAGE_GLOBAL | \
- _PAGE_MTMASK))
-
static inline int pud_present(pud_t pud)
{
return (pud_val(pud) & _PAGE_PRESENT);
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index b9e13a8fe2b7..414a0a919ef0 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -6,6 +6,11 @@
#ifndef _ASM_RISCV_PGTABLE_BITS_H
#define _ASM_RISCV_PGTABLE_BITS_H
+/*
+ * PTE format:
+ * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
+ * N MT[2] RSV & PFN reserved for SW D A G U X W R V
+ */
#define _PAGE_ACCESSED_OFFSET 6
#define _PAGE_PRESENT (1 << 0)
@@ -18,6 +23,54 @@
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#ifndef __ASSEMBLY__
+/*
+ * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions:
+ *
+ * 00 - PMA Normal Cacheable, No change to implied PMA memory type
+ * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
+ * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
+ * 11 - Rsvd Reserved for future standard use
+ */
+#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3))
+#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2))
+#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
+
+static inline ulong riscv_page_mtmask(void)
+{
+ ulong val;
+
+ ALT_SVPBMT(val, _PAGE_MTMASK);
+ return val;
+}
+
+static inline ulong riscv_page_nocache(void)
+{
+ ulong val;
+
+ ALT_SVPBMT(val, _PAGE_NOCACHE);
+ return val;
+}
+
+static inline ulong riscv_page_io(void)
+{
+ ulong val;
+
+ ALT_SVPBMT(val, _PAGE_IO);
+ return val;
+}
+
+#define _PAGE_NOCACHE riscv_page_nocache()
+#define _PAGE_IO riscv_page_io()
+#define _PAGE_MTMASK riscv_page_mtmask()
+
+/* Set of bits to preserve across pte_modify() */
+#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
+ _PAGE_WRITE | _PAGE_EXEC | \
+ _PAGE_USER | _PAGE_GLOBAL | \
+ _PAGE_MTMASK))
+#endif
+
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index edc68759b69d..5d5ba6513c14 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -8,7 +8,12 @@
#include <linux/mmzone.h>
#include <linux/sizes.h>
+#ifndef __ASSEMBLY__
+#include <linux/bits.h>
+#include <linux/const.h>
+#include <asm/errata_list.h>
+#endif
#include <asm/pgtable-bits.h>
#ifndef CONFIG_MMU
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h
2022-07-05 10:05 ` [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h guoren
@ 2022-07-08 6:10 ` Guo Ren
2022-07-08 9:03 ` Heiko Stübner
0 siblings, 1 reply; 14+ messages in thread
From: Guo Ren @ 2022-07-08 6:10 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-riscv, Guo Ren
Sorry all, I forgot this part. If you want to try, please care:
diff --git a/arch/riscv/include/asm/errata_list.h
b/arch/riscv/include/asm/errata_list.h
index 47175d91773d..b252068bfd3a 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -46,7 +46,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma",
SIFIVE_VENDOR_ID, \
* _val is marked as "will be overwritten", so need to set it to 0
* in the default case.
*/
-#define ALT_SVPBMT_SHIFT 61
+#define ALT_SVPBMT_SHIFT (__riscv_xlen-3)
#ifdef CONFIG_ERRATA_THEAD_PBMT
#define ALT_THEAD_PBMT_SHIFT 59
On Tue, Jul 5, 2022 at 6:05 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <guoren@linux.alibaba.com>
>
> This patch is preparation for rv32 svpbmt, which only moves the svpbmt
> bits definitions into the standard header and no other functionality
> modification. Here is the list of modification:
> - Change u64 to ulong of riscv_page_nocache/mtmask/io functions
> - Using __riscv_xlen instead of 64
>
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
> arch/riscv/include/asm/pgtable-32.h | 16 --------
> arch/riscv/include/asm/pgtable-64.h | 55 ---------------------------
> arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++
> arch/riscv/include/asm/pgtable.h | 5 +++
> 4 files changed, 58 insertions(+), 71 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> index 59ba1fbaf784..63b023bd4845 100644
> --- a/arch/riscv/include/asm/pgtable-32.h
> +++ b/arch/riscv/include/asm/pgtable-32.h
> @@ -7,8 +7,6 @@
> #define _ASM_RISCV_PGTABLE_32_H
>
> #include <asm-generic/pgtable-nopmd.h>
> -#include <linux/bits.h>
> -#include <linux/const.h>
>
> /* Size of region mapped by a page global directory */
> #define PGDIR_SHIFT 22
> @@ -17,20 +15,6 @@
>
> #define MAX_POSSIBLE_PHYSMEM_BITS 34
>
> -/*
> - * rv32 PTE format:
> - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> - * PFN reserved for SW D A G U X W R V
> - */
> #define _PAGE_PFN_MASK GENMASK(31, 10)
>
> -#define _PAGE_NOCACHE 0
> -#define _PAGE_IO 0
> -#define _PAGE_MTMASK 0
> -
> -/* Set of bits to preserve across pte_modify() */
> -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> - _PAGE_WRITE | _PAGE_EXEC | \
> - _PAGE_USER | _PAGE_GLOBAL))
> -
> #endif /* _ASM_RISCV_PGTABLE_32_H */
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 5c2aba5efbd0..3263b910e7d2 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -6,10 +6,6 @@
> #ifndef _ASM_RISCV_PGTABLE_64_H
> #define _ASM_RISCV_PGTABLE_64_H
>
> -#include <linux/bits.h>
> -#include <linux/const.h>
> -#include <asm/errata_list.h>
> -
> extern bool pgtable_l4_enabled;
> extern bool pgtable_l5_enabled;
>
> @@ -67,25 +63,8 @@ typedef struct {
>
> #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
>
> -/*
> - * rv64 PTE format:
> - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> - * N MT RSV PFN reserved for SW D A G U X W R V
> - */
> #define _PAGE_PFN_MASK GENMASK(53, 10)
>
> -/*
> - * [62:61] Svpbmt Memory Type definitions:
> - *
> - * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> - * 11 - Rsvd Reserved for future standard use
> - */
> -#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
> -#define _PAGE_IO_SVPBMT (1UL << 62)
> -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> -
> /*
> * [63:59] T-Head Memory Type definitions:
> *
> @@ -98,40 +77,6 @@ typedef struct {
> #define _PAGE_IO_THEAD (1UL << 63)
> #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> -static inline u64 riscv_page_mtmask(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_MTMASK);
> - return val;
> -}
> -
> -static inline u64 riscv_page_nocache(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_NOCACHE);
> - return val;
> -}
> -
> -static inline u64 riscv_page_io(void)
> -{
> - u64 val;
> -
> - ALT_SVPBMT(val, _PAGE_IO);
> - return val;
> -}
> -
> -#define _PAGE_NOCACHE riscv_page_nocache()
> -#define _PAGE_IO riscv_page_io()
> -#define _PAGE_MTMASK riscv_page_mtmask()
> -
> -/* Set of bits to preserve across pte_modify() */
> -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> - _PAGE_WRITE | _PAGE_EXEC | \
> - _PAGE_USER | _PAGE_GLOBAL | \
> - _PAGE_MTMASK))
> -
> static inline int pud_present(pud_t pud)
> {
> return (pud_val(pud) & _PAGE_PRESENT);
> diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> index b9e13a8fe2b7..414a0a919ef0 100644
> --- a/arch/riscv/include/asm/pgtable-bits.h
> +++ b/arch/riscv/include/asm/pgtable-bits.h
> @@ -6,6 +6,11 @@
> #ifndef _ASM_RISCV_PGTABLE_BITS_H
> #define _ASM_RISCV_PGTABLE_BITS_H
>
> +/*
> + * PTE format:
> + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> + * N MT[2] RSV & PFN reserved for SW D A G U X W R V
> + */
> #define _PAGE_ACCESSED_OFFSET 6
>
> #define _PAGE_PRESENT (1 << 0)
> @@ -18,6 +23,54 @@
> #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
> #define _PAGE_SOFT (1 << 8) /* Reserved for software */
>
> +#ifndef __ASSEMBLY__
> +/*
> + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions:
> + *
> + * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> + * 11 - Rsvd Reserved for future standard use
> + */
> +#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3))
> +#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2))
> +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> +
> +static inline ulong riscv_page_mtmask(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_MTMASK);
> + return val;
> +}
> +
> +static inline ulong riscv_page_nocache(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_NOCACHE);
> + return val;
> +}
> +
> +static inline ulong riscv_page_io(void)
> +{
> + ulong val;
> +
> + ALT_SVPBMT(val, _PAGE_IO);
> + return val;
> +}
> +
> +#define _PAGE_NOCACHE riscv_page_nocache()
> +#define _PAGE_IO riscv_page_io()
> +#define _PAGE_MTMASK riscv_page_mtmask()
> +
> +/* Set of bits to preserve across pte_modify() */
> +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> + _PAGE_WRITE | _PAGE_EXEC | \
> + _PAGE_USER | _PAGE_GLOBAL | \
> + _PAGE_MTMASK))
> +#endif
> +
> #define _PAGE_SPECIAL _PAGE_SOFT
> #define _PAGE_TABLE _PAGE_PRESENT
>
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index edc68759b69d..5d5ba6513c14 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -8,7 +8,12 @@
>
> #include <linux/mmzone.h>
> #include <linux/sizes.h>
> +#ifndef __ASSEMBLY__
> +#include <linux/bits.h>
> +#include <linux/const.h>
>
> +#include <asm/errata_list.h>
> +#endif
> #include <asm/pgtable-bits.h>
>
> #ifndef CONFIG_MMU
> --
> 2.36.1
>
--
Best Regards
Guo Ren
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h
2022-07-08 6:10 ` Guo Ren
@ 2022-07-08 9:03 ` Heiko Stübner
2022-07-08 9:49 ` Guo Ren
0 siblings, 1 reply; 14+ messages in thread
From: Heiko Stübner @ 2022-07-08 9:03 UTC (permalink / raw)
To: Palmer Dabbelt, linux-riscv; +Cc: linux-riscv, Guo Ren, Guo Ren
Hi Guo,
Am Freitag, 8. Juli 2022, 08:10:59 CEST schrieb Guo Ren:
> Sorry all, I forgot this part. If you want to try, please care:
>
> diff --git a/arch/riscv/include/asm/errata_list.h
> b/arch/riscv/include/asm/errata_list.h
> index 47175d91773d..b252068bfd3a 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -46,7 +46,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma",
> SIFIVE_VENDOR_ID, \
> * _val is marked as "will be overwritten", so need to set it to 0
> * in the default case.
> */
> -#define ALT_SVPBMT_SHIFT 61
> +#define ALT_SVPBMT_SHIFT (__riscv_xlen-3)
I think using explicit bit definitions might be nicer for this and not
result in surprises in the future?
i.e. doing a
#ifdef CONFIG_64BIT
#define ALT_SVPBMT_SHIFT 61
#else
...
similar to how the pgtable-xx.h gets included into pgtable.h
#ifdef CONFIG_64BIT
#include <asm/pgtable-64.h>
#else
#include <asm/pgtable-32.h>
#endif /* CONFIG_64BIT */
Heiko
> #ifdef CONFIG_ERRATA_THEAD_PBMT
> #define ALT_THEAD_PBMT_SHIFT 59
>
> On Tue, Jul 5, 2022 at 6:05 PM <guoren@kernel.org> wrote:
> >
> > From: Guo Ren <guoren@linux.alibaba.com>
> >
> > This patch is preparation for rv32 svpbmt, which only moves the svpbmt
> > bits definitions into the standard header and no other functionality
> > modification. Here is the list of modification:
> > - Change u64 to ulong of riscv_page_nocache/mtmask/io functions
> > - Using __riscv_xlen instead of 64
> >
> > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > Signed-off-by: Guo Ren <guoren@kernel.org>
> > ---
> > arch/riscv/include/asm/pgtable-32.h | 16 --------
> > arch/riscv/include/asm/pgtable-64.h | 55 ---------------------------
> > arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++
> > arch/riscv/include/asm/pgtable.h | 5 +++
> > 4 files changed, 58 insertions(+), 71 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> > index 59ba1fbaf784..63b023bd4845 100644
> > --- a/arch/riscv/include/asm/pgtable-32.h
> > +++ b/arch/riscv/include/asm/pgtable-32.h
> > @@ -7,8 +7,6 @@
> > #define _ASM_RISCV_PGTABLE_32_H
> >
> > #include <asm-generic/pgtable-nopmd.h>
> > -#include <linux/bits.h>
> > -#include <linux/const.h>
> >
> > /* Size of region mapped by a page global directory */
> > #define PGDIR_SHIFT 22
> > @@ -17,20 +15,6 @@
> >
> > #define MAX_POSSIBLE_PHYSMEM_BITS 34
> >
> > -/*
> > - * rv32 PTE format:
> > - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > - * PFN reserved for SW D A G U X W R V
> > - */
> > #define _PAGE_PFN_MASK GENMASK(31, 10)
> >
> > -#define _PAGE_NOCACHE 0
> > -#define _PAGE_IO 0
> > -#define _PAGE_MTMASK 0
> > -
> > -/* Set of bits to preserve across pte_modify() */
> > -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > - _PAGE_WRITE | _PAGE_EXEC | \
> > - _PAGE_USER | _PAGE_GLOBAL))
> > -
> > #endif /* _ASM_RISCV_PGTABLE_32_H */
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index 5c2aba5efbd0..3263b910e7d2 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -6,10 +6,6 @@
> > #ifndef _ASM_RISCV_PGTABLE_64_H
> > #define _ASM_RISCV_PGTABLE_64_H
> >
> > -#include <linux/bits.h>
> > -#include <linux/const.h>
> > -#include <asm/errata_list.h>
> > -
> > extern bool pgtable_l4_enabled;
> > extern bool pgtable_l5_enabled;
> >
> > @@ -67,25 +63,8 @@ typedef struct {
> >
> > #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
> >
> > -/*
> > - * rv64 PTE format:
> > - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > - * N MT RSV PFN reserved for SW D A G U X W R V
> > - */
> > #define _PAGE_PFN_MASK GENMASK(53, 10)
> >
> > -/*
> > - * [62:61] Svpbmt Memory Type definitions:
> > - *
> > - * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> > - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> > - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> > - * 11 - Rsvd Reserved for future standard use
> > - */
> > -#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
> > -#define _PAGE_IO_SVPBMT (1UL << 62)
> > -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> > -
> > /*
> > * [63:59] T-Head Memory Type definitions:
> > *
> > @@ -98,40 +77,6 @@ typedef struct {
> > #define _PAGE_IO_THEAD (1UL << 63)
> > #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
> >
> > -static inline u64 riscv_page_mtmask(void)
> > -{
> > - u64 val;
> > -
> > - ALT_SVPBMT(val, _PAGE_MTMASK);
> > - return val;
> > -}
> > -
> > -static inline u64 riscv_page_nocache(void)
> > -{
> > - u64 val;
> > -
> > - ALT_SVPBMT(val, _PAGE_NOCACHE);
> > - return val;
> > -}
> > -
> > -static inline u64 riscv_page_io(void)
> > -{
> > - u64 val;
> > -
> > - ALT_SVPBMT(val, _PAGE_IO);
> > - return val;
> > -}
> > -
> > -#define _PAGE_NOCACHE riscv_page_nocache()
> > -#define _PAGE_IO riscv_page_io()
> > -#define _PAGE_MTMASK riscv_page_mtmask()
> > -
> > -/* Set of bits to preserve across pte_modify() */
> > -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > - _PAGE_WRITE | _PAGE_EXEC | \
> > - _PAGE_USER | _PAGE_GLOBAL | \
> > - _PAGE_MTMASK))
> > -
> > static inline int pud_present(pud_t pud)
> > {
> > return (pud_val(pud) & _PAGE_PRESENT);
> > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > index b9e13a8fe2b7..414a0a919ef0 100644
> > --- a/arch/riscv/include/asm/pgtable-bits.h
> > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > @@ -6,6 +6,11 @@
> > #ifndef _ASM_RISCV_PGTABLE_BITS_H
> > #define _ASM_RISCV_PGTABLE_BITS_H
> >
> > +/*
> > + * PTE format:
> > + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > + * N MT[2] RSV & PFN reserved for SW D A G U X W R V
> > + */
> > #define _PAGE_ACCESSED_OFFSET 6
> >
> > #define _PAGE_PRESENT (1 << 0)
> > @@ -18,6 +23,54 @@
> > #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
> > #define _PAGE_SOFT (1 << 8) /* Reserved for software */
> >
> > +#ifndef __ASSEMBLY__
> > +/*
> > + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions:
> > + *
> > + * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> > + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> > + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> > + * 11 - Rsvd Reserved for future standard use
> > + */
> > +#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3))
> > +#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2))
> > +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> > +
> > +static inline ulong riscv_page_mtmask(void)
> > +{
> > + ulong val;
> > +
> > + ALT_SVPBMT(val, _PAGE_MTMASK);
> > + return val;
> > +}
> > +
> > +static inline ulong riscv_page_nocache(void)
> > +{
> > + ulong val;
> > +
> > + ALT_SVPBMT(val, _PAGE_NOCACHE);
> > + return val;
> > +}
> > +
> > +static inline ulong riscv_page_io(void)
> > +{
> > + ulong val;
> > +
> > + ALT_SVPBMT(val, _PAGE_IO);
> > + return val;
> > +}
> > +
> > +#define _PAGE_NOCACHE riscv_page_nocache()
> > +#define _PAGE_IO riscv_page_io()
> > +#define _PAGE_MTMASK riscv_page_mtmask()
> > +
> > +/* Set of bits to preserve across pte_modify() */
> > +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > + _PAGE_WRITE | _PAGE_EXEC | \
> > + _PAGE_USER | _PAGE_GLOBAL | \
> > + _PAGE_MTMASK))
> > +#endif
> > +
> > #define _PAGE_SPECIAL _PAGE_SOFT
> > #define _PAGE_TABLE _PAGE_PRESENT
> >
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index edc68759b69d..5d5ba6513c14 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -8,7 +8,12 @@
> >
> > #include <linux/mmzone.h>
> > #include <linux/sizes.h>
> > +#ifndef __ASSEMBLY__
> > +#include <linux/bits.h>
> > +#include <linux/const.h>
> >
> > +#include <asm/errata_list.h>
> > +#endif
> > #include <asm/pgtable-bits.h>
> >
> > #ifndef CONFIG_MMU
> > --
> > 2.36.1
> >
>
>
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h
2022-07-08 9:03 ` Heiko Stübner
@ 2022-07-08 9:49 ` Guo Ren
0 siblings, 0 replies; 14+ messages in thread
From: Guo Ren @ 2022-07-08 9:49 UTC (permalink / raw)
To: Heiko Stübner; +Cc: Palmer Dabbelt, linux-riscv, Guo Ren
On Fri, Jul 8, 2022 at 5:03 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Guo,
>
> Am Freitag, 8. Juli 2022, 08:10:59 CEST schrieb Guo Ren:
> > Sorry all, I forgot this part. If you want to try, please care:
> >
> > diff --git a/arch/riscv/include/asm/errata_list.h
> > b/arch/riscv/include/asm/errata_list.h
> > index 47175d91773d..b252068bfd3a 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -46,7 +46,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma",
> > SIFIVE_VENDOR_ID, \
> > * _val is marked as "will be overwritten", so need to set it to 0
> > * in the default case.
> > */
> > -#define ALT_SVPBMT_SHIFT 61
> > +#define ALT_SVPBMT_SHIFT (__riscv_xlen-3)
>
> I think using explicit bit definitions might be nicer for this and not
> result in surprises in the future?
>
> i.e. doing a
> #ifdef CONFIG_64BIT
> #define ALT_SVPBMT_SHIFT 61
> #else
> ...
>
> similar to how the pgtable-xx.h gets included into pgtable.h
Good point, I would avoid __riscv_xlen in the next version.
>
> #ifdef CONFIG_64BIT
> #include <asm/pgtable-64.h>
> #else
> #include <asm/pgtable-32.h>
> #endif /* CONFIG_64BIT */
>
>
> Heiko
>
> > #ifdef CONFIG_ERRATA_THEAD_PBMT
> > #define ALT_THEAD_PBMT_SHIFT 59
> >
> > On Tue, Jul 5, 2022 at 6:05 PM <guoren@kernel.org> wrote:
> > >
> > > From: Guo Ren <guoren@linux.alibaba.com>
> > >
> > > This patch is preparation for rv32 svpbmt, which only moves the svpbmt
> > > bits definitions into the standard header and no other functionality
> > > modification. Here is the list of modification:
> > > - Change u64 to ulong of riscv_page_nocache/mtmask/io functions
> > > - Using __riscv_xlen instead of 64
> > >
> > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> > > Signed-off-by: Guo Ren <guoren@kernel.org>
> > > ---
> > > arch/riscv/include/asm/pgtable-32.h | 16 --------
> > > arch/riscv/include/asm/pgtable-64.h | 55 ---------------------------
> > > arch/riscv/include/asm/pgtable-bits.h | 53 ++++++++++++++++++++++++++
> > > arch/riscv/include/asm/pgtable.h | 5 +++
> > > 4 files changed, 58 insertions(+), 71 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> > > index 59ba1fbaf784..63b023bd4845 100644
> > > --- a/arch/riscv/include/asm/pgtable-32.h
> > > +++ b/arch/riscv/include/asm/pgtable-32.h
> > > @@ -7,8 +7,6 @@
> > > #define _ASM_RISCV_PGTABLE_32_H
> > >
> > > #include <asm-generic/pgtable-nopmd.h>
> > > -#include <linux/bits.h>
> > > -#include <linux/const.h>
> > >
> > > /* Size of region mapped by a page global directory */
> > > #define PGDIR_SHIFT 22
> > > @@ -17,20 +15,6 @@
> > >
> > > #define MAX_POSSIBLE_PHYSMEM_BITS 34
> > >
> > > -/*
> > > - * rv32 PTE format:
> > > - * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > > - * PFN reserved for SW D A G U X W R V
> > > - */
> > > #define _PAGE_PFN_MASK GENMASK(31, 10)
> > >
> > > -#define _PAGE_NOCACHE 0
> > > -#define _PAGE_IO 0
> > > -#define _PAGE_MTMASK 0
> > > -
> > > -/* Set of bits to preserve across pte_modify() */
> > > -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > > - _PAGE_WRITE | _PAGE_EXEC | \
> > > - _PAGE_USER | _PAGE_GLOBAL))
> > > -
> > > #endif /* _ASM_RISCV_PGTABLE_32_H */
> > > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > > index 5c2aba5efbd0..3263b910e7d2 100644
> > > --- a/arch/riscv/include/asm/pgtable-64.h
> > > +++ b/arch/riscv/include/asm/pgtable-64.h
> > > @@ -6,10 +6,6 @@
> > > #ifndef _ASM_RISCV_PGTABLE_64_H
> > > #define _ASM_RISCV_PGTABLE_64_H
> > >
> > > -#include <linux/bits.h>
> > > -#include <linux/const.h>
> > > -#include <asm/errata_list.h>
> > > -
> > > extern bool pgtable_l4_enabled;
> > > extern bool pgtable_l5_enabled;
> > >
> > > @@ -67,25 +63,8 @@ typedef struct {
> > >
> > > #define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t))
> > >
> > > -/*
> > > - * rv64 PTE format:
> > > - * | 63 | 62 61 | 60 54 | 53 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > > - * N MT RSV PFN reserved for SW D A G U X W R V
> > > - */
> > > #define _PAGE_PFN_MASK GENMASK(53, 10)
> > >
> > > -/*
> > > - * [62:61] Svpbmt Memory Type definitions:
> > > - *
> > > - * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> > > - * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> > > - * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> > > - * 11 - Rsvd Reserved for future standard use
> > > - */
> > > -#define _PAGE_NOCACHE_SVPBMT (1UL << 61)
> > > -#define _PAGE_IO_SVPBMT (1UL << 62)
> > > -#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> > > -
> > > /*
> > > * [63:59] T-Head Memory Type definitions:
> > > *
> > > @@ -98,40 +77,6 @@ typedef struct {
> > > #define _PAGE_IO_THEAD (1UL << 63)
> > > #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
> > >
> > > -static inline u64 riscv_page_mtmask(void)
> > > -{
> > > - u64 val;
> > > -
> > > - ALT_SVPBMT(val, _PAGE_MTMASK);
> > > - return val;
> > > -}
> > > -
> > > -static inline u64 riscv_page_nocache(void)
> > > -{
> > > - u64 val;
> > > -
> > > - ALT_SVPBMT(val, _PAGE_NOCACHE);
> > > - return val;
> > > -}
> > > -
> > > -static inline u64 riscv_page_io(void)
> > > -{
> > > - u64 val;
> > > -
> > > - ALT_SVPBMT(val, _PAGE_IO);
> > > - return val;
> > > -}
> > > -
> > > -#define _PAGE_NOCACHE riscv_page_nocache()
> > > -#define _PAGE_IO riscv_page_io()
> > > -#define _PAGE_MTMASK riscv_page_mtmask()
> > > -
> > > -/* Set of bits to preserve across pte_modify() */
> > > -#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > > - _PAGE_WRITE | _PAGE_EXEC | \
> > > - _PAGE_USER | _PAGE_GLOBAL | \
> > > - _PAGE_MTMASK))
> > > -
> > > static inline int pud_present(pud_t pud)
> > > {
> > > return (pud_val(pud) & _PAGE_PRESENT);
> > > diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
> > > index b9e13a8fe2b7..414a0a919ef0 100644
> > > --- a/arch/riscv/include/asm/pgtable-bits.h
> > > +++ b/arch/riscv/include/asm/pgtable-bits.h
> > > @@ -6,6 +6,11 @@
> > > #ifndef _ASM_RISCV_PGTABLE_BITS_H
> > > #define _ASM_RISCV_PGTABLE_BITS_H
> > >
> > > +/*
> > > + * PTE format:
> > > + * | XLEN-1 | XLEN-2 XLEN-3 | XLEN-4 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > > + * N MT[2] RSV & PFN reserved for SW D A G U X W R V
> > > + */
> > > #define _PAGE_ACCESSED_OFFSET 6
> > >
> > > #define _PAGE_PRESENT (1 << 0)
> > > @@ -18,6 +23,54 @@
> > > #define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
> > > #define _PAGE_SOFT (1 << 8) /* Reserved for software */
> > >
> > > +#ifndef __ASSEMBLY__
> > > +/*
> > > + * [XLEN-2:XLEN-3] Svpbmt Memory Type definitions:
> > > + *
> > > + * 00 - PMA Normal Cacheable, No change to implied PMA memory type
> > > + * 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
> > > + * 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
> > > + * 11 - Rsvd Reserved for future standard use
> > > + */
> > > +#define _PAGE_NOCACHE_SVPBMT (1UL << (__riscv_xlen-3))
> > > +#define _PAGE_IO_SVPBMT (1UL << (__riscv_xlen-2))
> > > +#define _PAGE_MTMASK_SVPBMT (_PAGE_NOCACHE_SVPBMT | _PAGE_IO_SVPBMT)
> > > +
> > > +static inline ulong riscv_page_mtmask(void)
> > > +{
> > > + ulong val;
> > > +
> > > + ALT_SVPBMT(val, _PAGE_MTMASK);
> > > + return val;
> > > +}
> > > +
> > > +static inline ulong riscv_page_nocache(void)
> > > +{
> > > + ulong val;
> > > +
> > > + ALT_SVPBMT(val, _PAGE_NOCACHE);
> > > + return val;
> > > +}
> > > +
> > > +static inline ulong riscv_page_io(void)
> > > +{
> > > + ulong val;
> > > +
> > > + ALT_SVPBMT(val, _PAGE_IO);
> > > + return val;
> > > +}
> > > +
> > > +#define _PAGE_NOCACHE riscv_page_nocache()
> > > +#define _PAGE_IO riscv_page_io()
> > > +#define _PAGE_MTMASK riscv_page_mtmask()
> > > +
> > > +/* Set of bits to preserve across pte_modify() */
> > > +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
> > > + _PAGE_WRITE | _PAGE_EXEC | \
> > > + _PAGE_USER | _PAGE_GLOBAL | \
> > > + _PAGE_MTMASK))
> > > +#endif
> > > +
> > > #define _PAGE_SPECIAL _PAGE_SOFT
> > > #define _PAGE_TABLE _PAGE_PRESENT
> > >
> > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > > index edc68759b69d..5d5ba6513c14 100644
> > > --- a/arch/riscv/include/asm/pgtable.h
> > > +++ b/arch/riscv/include/asm/pgtable.h
> > > @@ -8,7 +8,12 @@
> > >
> > > #include <linux/mmzone.h>
> > > #include <linux/sizes.h>
> > > +#ifndef __ASSEMBLY__
> > > +#include <linux/bits.h>
> > > +#include <linux/const.h>
> > >
> > > +#include <asm/errata_list.h>
> > > +#endif
> > > #include <asm/pgtable-bits.h>
> > >
> > > #ifndef CONFIG_MMU
> > > --
> > > 2.36.1
> > >
> >
> >
> >
>
>
>
>
--
Best Regards
Guo Ren
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [RFC PATCH 4/4] riscv: Change rv32p34 to rv32p31 for svpbmt
2022-07-05 10:05 [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support guoren
` (2 preceding siblings ...)
2022-07-05 10:05 ` [RFC PATCH 3/4] riscv: pgtable: Move svpbmt into the common pgtable-bits.h guoren
@ 2022-07-05 10:05 ` guoren
2022-07-05 17:22 ` [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support Christoph Hellwig
4 siblings, 0 replies; 14+ messages in thread
From: guoren @ 2022-07-05 10:05 UTC (permalink / raw)
To: palmer; +Cc: linux-riscv, Guo Ren, Guo Ren
From: Guo Ren <guoren@linux.alibaba.com>
Decrease rv32 16GB physical address range to 2GB (rv32p34 -> rv32p31)
for svpbmt support. Svpbmt & napot could directly occupy rv32 PPN
highest bits. The patch wouldn't reduce the functionality of rv32-Linux,
because rv32-Linux only supports 1GB direct mapping (0xc0000000 -
0xffffffff). So 2GB physical address range is enough for current
rv32-Linux (1GB for memory, 1GB for IO).
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/pgtable-32.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 32ffef9f6e5b..0dc1509e7e1c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -360,7 +360,7 @@ config RISCV_ISA_C
config RISCV_ISA_SVPBMT
bool "SVPBMT extension support"
- depends on 64BIT && MMU
+ depends on MMU
select RISCV_ALTERNATIVE
default y
help
diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
index 63b023bd4845..aa94f6487670 100644
--- a/arch/riscv/include/asm/pgtable-32.h
+++ b/arch/riscv/include/asm/pgtable-32.h
@@ -13,8 +13,8 @@
#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE - 1))
-#define MAX_POSSIBLE_PHYSMEM_BITS 34
+#define MAX_POSSIBLE_PHYSMEM_BITS 31
-#define _PAGE_PFN_MASK GENMASK(31, 10)
+#define _PAGE_PFN_MASK GENMASK(28, 10)
#endif /* _ASM_RISCV_PGTABLE_32_H */
--
2.36.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support
2022-07-05 10:05 [RFC PATCH 0/4] Proof of concept for rv32 svpbmt support guoren
` (3 preceding siblings ...)
2022-07-05 10:05 ` [RFC PATCH 4/4] riscv: Change rv32p34 to rv32p31 for svpbmt guoren
@ 2022-07-05 17:22 ` Christoph Hellwig
4 siblings, 0 replies; 14+ messages in thread
From: Christoph Hellwig @ 2022-07-05 17:22 UTC (permalink / raw)
To: guoren; +Cc: palmer, linux-riscv, Guo Ren
On Tue, Jul 05, 2022 at 06:05:19AM -0400, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
>
> Make rv32 support svpbmt & napot by reducing the PPN witdth (sv32p34 ->
> sv32p31).
Yeah, the lack of rv32 in svpbmt was a very odd choice, given that
non-coherent DMA is most common in crappy low end devices.
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^ permalink raw reply [flat|nested] 14+ messages in thread