From: Paul Walmsley <paul.walmsley@sifive.com>
To: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, Atish Patra <Atish.Patra@wdc.com>,
Greg KH <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, alexios.zavras@intel.com,
yash.shah@sifive.com, robh+dt@kernel.org, tglx@linutronix.de,
bmeng.cn@gmail.com, linux-riscv@lists.infradead.org,
allison@lohutok.net
Subject: Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled
Date: Sun, 15 Dec 2019 11:56:23 -0800 (PST) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1912151155010.64438@viisi.sifive.com> (raw)
In-Reply-To: <mhng-a1ba4b8a-4c6a-43e9-a87a-f8bbbe3555d8@palmerdabbelt-glaptop>
On Fri, 13 Dec 2019, Palmer Dabbelt wrote:
> I thought the plan was to get this stuff out of arch/riscv? It looks like it
> only got half-way done.
That's still the plan. Will probably send that one upstream in v5.5-rc.
Am not a huge fan of moving it to drivers/soc, for a few different
reasons, but some people seem to feel very passionately about it.
- Paul
next prev parent reply other threads:[~2019-12-15 19:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-09 11:25 [PATCH 0/2] L2 ccache DT and cacheinfo support to read no. of L2 cache ways enabled Yash Shah
2019-12-09 11:25 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Yash Shah
2019-12-09 11:25 ` [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled Yash Shah
2019-12-14 2:12 ` Palmer Dabbelt
2019-12-15 19:56 ` Paul Walmsley [this message]
2019-12-23 8:53 ` Yash Shah
2019-12-14 2:13 ` [PATCH 1/2] riscv: dts: Add DT support for SiFive L2 cache controller Palmer Dabbelt
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