* [PATCH 1/6] mbox: add polarfire soc system controller mailbox
@ 2020-11-19 17:04 conor.dooley
2020-11-20 0:05 ` Damien Le Moal
0 siblings, 1 reply; 5+ messages in thread
From: conor.dooley @ 2020-11-19 17:04 UTC (permalink / raw)
To: robh+dt, jassisinghbrar, aou, paul.walmsley, palmer, devicetree,
linux-riscv
Cc: cyril.jean, david.abdurachmanov, daire.mcnamara, anup.patel,
atish.patra, Conor Dooley, lewis.hanly
From: Conor Dooley <conor.dooley@microchip.com>
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/mailbox/Kconfig | 12 ++
drivers/mailbox/Makefile | 2 +
drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++
3 files changed, 310 insertions(+)
create mode 100644 drivers/mailbox/mailbox-mpfs.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 05b1009e2820..4881a519683a 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -153,6 +153,18 @@ config MAILBOX_TEST
Test client to help with testing new Controller driver
implementations.
+config MPFS_MBOX
+ tristate "MPFS Mailbox"
+ depends on HAS_IOMEM
+ depends on SOC_MICROCHIP_POLARFIRE
+ help
+ This driver adds support for the Polarfire SoC mailbox controller.
+
+ To compile this driver as a module, choose M here. the
+ module will be called mailbox-mpfs.
+
+ If unsure, say Y.
+
config QCOM_APCS_IPC
tristate "Qualcomm APCS IPC driver"
depends on ARCH_QCOM || COMPILE_TEST
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 2e06e02b2e03..63f49b5bcc43 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
+obj-$(CONFIG_MPFS_MBOX) += mailbox-mpfs.o
+
obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
new file mode 100644
index 000000000000..686ccd3317f9
--- /dev/null
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -0,0 +1,296 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Microchip MPFS system controller/mailbox controller driver
+ *
+ * Copyright (c) 2020 Microchip Corporation. All rights reserved.
+ *
+ * Author: Conor Dooley <conor.dooley@microchip.com>
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mailbox_controller.h>
+#include <soc/microchip/mpfs.h>
+
+#define SERVICES_CR_OFFSET 0x50u
+#define SERVICES_SR_OFFSET 0x54u
+#define MAILBOX_REG_OFFSET 0x800u
+#define MSS_SYS_SUCCESS 0u
+#define MSS_SYS_BUSY 0xefu
+#define MSS_SYS_PARAM_ERR 0xffu
+#define MSS_SYS_MAILBOX_DATA_OFFSET 0u
+
+/***************SCBCTRL SERVICES_CR register*************************/
+
+#define SCBCTRL_SERVICESCR_REQ (0u)
+#define SCBCTRL_SERVICESCR_REQ_MASK BIT(SCBCTRL_SERVICESCR_REQ)
+
+#define SCBCTRL_SERVICESCR_BUSY (1u)
+#define SCBCTRL_SERVICESCR_BUSY_MASK BIT(SCBCTRL_SERVICESCR_BUSY)
+
+#define SCBCTRL_SERVICESCR_ABORT (2u)
+#define SCBCTRL_SERVICESCR_ABORT_MASK BIT(SCBCTRL_SERVICESCR_ABORT)
+
+#define SCBCTRL_SERVICESCR_NOTIFY (3u)
+#define SCBCTRL_SERVICESCR_NOTIFY_MASK BIT(SCBCTRL_SERVICESCR_NOTIFY)
+
+#define SCBCTRL_SERVICESCR_COMMAND (16u)
+#define SCBCTRL_SERVICESCR_COMMAND_MASK (0xffffu << SCBCTRL_SERVICESCR_COMMAND)
+
+/***************SCBCTRL SERVICES_SR registers*************************/
+
+#define SCBCTRL_SERVICESSR_REQ (0u)
+#define SCBCTRL_SERVICESSR_REQ_MASK BIT(SCBCTRL_SERVICESSR_REQ)
+
+#define SCBCTRL_SERVICESSR_BUSY (1u)
+#define SCBCTRL_SERVICESSR_BUSY_MASK BIT(SCBCTRL_SERVICESSR_BUSY)
+
+#define SCBCTRL_SERVICESSR_ABORT (2u)
+#define SCBCTRL_SERVICESSR_ABORT_MASK BIT(SCBCTRL_SERVICESSR_ABORT)
+
+#define SCBCTRL_SERVICESSR_NOTIFY (3u)
+#define SCBCTRL_SERVICESSR_NOTIFY_MASK BIT(SCBCTRL_SERVICESSR_NOTIFY)
+
+#define SCBCTRL_SERVICESSR_STATUS (16u)
+#define SCBCTRL_SERVICESSR_STATUS_MASK (0xffffu << SCBCTRL_SERVICESSR_STATUS)
+
+struct mpfs_mbox {
+ struct mbox_controller controller;
+ struct device *dev;
+ int irq;
+ void __iomem *mailbox_base;
+ void __iomem *int_reg;
+ struct mbox_chan *chan;
+ u16 response_size;
+ u16 response_offset;
+};
+
+static int mpfs_mbox_busy(struct mpfs_mbox *mbox)
+{
+ u32 status;
+
+ status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET);
+
+ return status & SCBCTRL_SERVICESSR_BUSY_MASK;
+}
+
+static struct mpfs_mbox *mbox_chan_to_mpfs_mbox(struct mbox_chan *chan)
+{
+ if (!chan || !chan->con_priv)
+ return NULL;
+
+ return (struct mpfs_mbox *)chan->con_priv;
+}
+
+static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ u32 index;
+ u32 *word_buf;
+ u8 *byte_buf;
+ u8 byte_off;
+ u8 byte_index;
+ u32 mailbox_val = 0u;
+ u16 mb_offset;
+ u16 mbox_options_select;
+ u32 mbox_tx_trigger;
+
+ struct mpfs_mss_msg *msg = data;
+
+ struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
+
+ mb_offset = msg->mailbox_offset;
+ mbox->response_size = msg->response_size;
+ mbox->response_offset = msg->response_offset;
+
+ mbox_options_select = ((mb_offset << 7u) | (msg->cmd_opcode & 0x7fu));
+ mbox_tx_trigger = (((mbox_options_select << SCBCTRL_SERVICESCR_COMMAND) &
+ SCBCTRL_SERVICESCR_COMMAND_MASK) |
+ SCBCTRL_SERVICESCR_REQ_MASK | SCBCTRL_SERVICESSR_NOTIFY_MASK);
+
+ if (mpfs_mbox_busy(mbox))
+ return MSS_SYS_BUSY;
+
+ /* Code for MSS_SYS_PARAM_ERR is not implemented with this version of driver. */
+
+ writel_relaxed(0x0U, mbox->int_reg);
+
+ if (msg->cmd_data_size > 0u) {
+ byte_buf = (u8 *)(msg->cmd_data);
+
+ for (index = 0u; index < (msg->cmd_data_size / 4u); index++) {
+ writel_relaxed(word_buf[index],
+ mbox->mailbox_base + MAILBOX_REG_OFFSET + index);
+ }
+
+ if ((msg->cmd_data_size % 4u) > 0u) {
+ byte_off = (((msg->cmd_data_size / 4u) * 4u));
+ byte_buf = (u8 *)(msg->cmd_data + byte_off);
+
+ mailbox_val = readl_relaxed(mbox->mailbox_base +
+ MAILBOX_REG_OFFSET + index);
+
+ for (byte_index = 0u;
+ byte_index < (msg->cmd_data_size % 4u);
+ byte_index++) {
+ mailbox_val &= ~(0xffu << (byte_index * 8u));
+ mailbox_val |= (byte_buf[byte_index]
+ << (byte_index * 8u));
+ }
+
+ writel_relaxed(mailbox_val,
+ mbox->mailbox_base + MAILBOX_REG_OFFSET + index);
+ }
+ }
+
+ writel_relaxed(mbox_tx_trigger, mbox->mailbox_base + SERVICES_CR_OFFSET);
+
+ return MSS_SYS_SUCCESS;
+}
+
+static inline int mpfs_mbox_pending(struct mpfs_mbox *mbox)
+{
+ u32 status;
+
+ status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET);
+
+ return !(status & SCBCTRL_SERVICESSR_BUSY_MASK);
+}
+
+static void mpfs_mbox_rx_data(struct mbox_chan *chan)
+{
+ struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
+ u32 *data;
+ u32 index;
+ u32 response_limit;
+
+ data = devm_kzalloc(mbox->dev, sizeof(*data) * mbox->response_size,
+ GFP_ATOMIC);
+
+ response_limit = (mbox->response_size) + (mbox->response_offset);
+ if (mpfs_mbox_pending(mbox) && mbox->response_size > 0U) {
+ for (index = (mbox->response_offset); index < response_limit;
+ index++) {
+ data[index - (mbox->response_offset)] =
+ readl_relaxed(mbox->mailbox_base + MAILBOX_REG_OFFSET +
+ index * 0x4);
+ }
+ }
+
+ mbox_chan_received_data(chan, (void *)data);
+ devm_kfree(mbox->dev, data);
+}
+
+static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
+{
+ struct mbox_chan *chan = (struct mbox_chan *)data;
+ struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
+
+ writel_relaxed(0x0U, mbox->int_reg);
+
+ mpfs_mbox_rx_data(chan);
+
+ mbox_chan_txdone(chan, 0);
+ return IRQ_HANDLED;
+}
+
+static int mpfs_mbox_startup(struct mbox_chan *chan)
+{
+ struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
+ int ret = 0;
+
+ if (!mbox)
+ return -EINVAL;
+ ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0,
+ "mpfs-mailbox", chan);
+ if (unlikely(ret)) {
+ dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n",
+ ret);
+ return ret;
+ }
+
+ return ret;
+}
+
+static void mpfs_mbox_shutdown(struct mbox_chan *chan)
+{
+ struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
+
+ devm_free_irq(mbox->dev, mbox->irq, chan);
+}
+
+static const struct mbox_chan_ops mpfs_mbox_ops = {
+ .send_data = mpfs_mbox_send_data,
+ .startup = mpfs_mbox_startup,
+ .shutdown = mpfs_mbox_shutdown,
+};
+
+static int mpfs_mbox_probe(struct platform_device *pdev)
+{
+ struct mpfs_mbox *mbox;
+ struct resource *regs;
+ struct mbox_chan *chans;
+ int ret;
+
+ mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
+ if (!mbox)
+ return -ENOMEM;
+
+ chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
+ if (!chans)
+ return -ENOMEM;
+
+ mbox->mailbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
+ if (IS_ERR(mbox->mailbox_base))
+ return PTR_ERR(mbox->mailbox_base);
+
+ mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s);
+ if (IS_ERR(mbox->int_reg))
+ return PTR_ERR(mbox->int_reg);
+
+ mbox->irq = platform_get_irq(pdev, 0);
+
+ mbox->dev = &pdev->dev;
+
+ chans[0].con_priv = mbox;
+ mbox->controller.dev = mbox->dev;
+ mbox->controller.num_chans = 1;
+ mbox->controller.chans = chans;
+ mbox->controller.ops = &mpfs_mbox_ops;
+ mbox->controller.txdone_irq = true;
+
+ ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
+ if (ret) {
+ dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
+ return -1;
+ }
+ dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");
+
+ return 0;
+}
+
+static const struct of_device_id mpfs_mbox_of_match[] = {
+ {
+ .compatible = "microchip,polarfire-soc-mailbox",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
+
+static struct platform_driver mpfs_mbox_driver = {
+ .driver = {
+ .name = "mpfs-mailbox",
+ .of_match_table = mpfs_mbox_of_match,
+ },
+ .probe = mpfs_mbox_probe,
+};
+module_platform_driver(mpfs_mbox_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("MPFS mailbox controller driver");
--
2.17.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/6] mbox: add polarfire soc system controller mailbox
2020-11-19 17:04 [PATCH 1/6] mbox: add polarfire soc system controller mailbox conor.dooley
@ 2020-11-20 0:05 ` Damien Le Moal
2020-11-30 13:23 ` Conor.Dooley
0 siblings, 1 reply; 5+ messages in thread
From: Damien Le Moal @ 2020-11-20 0:05 UTC (permalink / raw)
To: conor.dooley, robh+dt, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: cyril.jean, david.abdurachmanov, daire.mcnamara, Anup Patel,
Atish Patra, lewis.hanly
On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> This driver adds support for the single mailbox channel of the MSS
> system controller on the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> drivers/mailbox/Kconfig | 12 ++
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++
> 3 files changed, 310 insertions(+)
> create mode 100644 drivers/mailbox/mailbox-mpfs.c
>
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index 05b1009e2820..4881a519683a 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -153,6 +153,18 @@ config MAILBOX_TEST
> Test client to help with testing new Controller driver
> implementations.
>
> +config MPFS_MBOX
> + tristate "MPFS Mailbox"
> + depends on HAS_IOMEM
Shouldn't this dependency be on SOC_MICROCHIP_POLARFIRE ?
> + depends on SOC_MICROCHIP_POLARFIRE
> + help
> + This driver adds support for the Polarfire SoC mailbox controller.
> +
> + To compile this driver as a module, choose M here. the
> + module will be called mailbox-mpfs.
> +
> + If unsure, say Y.
> +
> config QCOM_APCS_IPC
> tristate "Qualcomm APCS IPC driver"
> depends on ARCH_QCOM || COMPILE_TEST
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index 2e06e02b2e03..63f49b5bcc43 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
>
> obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
>
> +obj-$(CONFIG_MPFS_MBOX) += mailbox-mpfs.o
> +
> obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
>
> obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
> new file mode 100644
> index 000000000000..686ccd3317f9
> --- /dev/null
> +++ b/drivers/mailbox/mailbox-mpfs.c
> @@ -0,0 +1,296 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Microchip MPFS system controller/mailbox controller driver
> + *
> + * Copyright (c) 2020 Microchip Corporation. All rights reserved.
> + *
> + * Author: Conor Dooley <conor.dooley@microchip.com>
> + *
> + */
> +
> +#include <linux/io.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/mailbox_controller.h>
> +#include <soc/microchip/mpfs.h>
> +
> +#define SERVICES_CR_OFFSET 0x50u
> +#define SERVICES_SR_OFFSET 0x54u
> +#define MAILBOX_REG_OFFSET 0x800u
> +#define MSS_SYS_SUCCESS 0u
Is this really necessary ?
> +#define MSS_SYS_BUSY 0xefu
> +#define MSS_SYS_PARAM_ERR 0xffu
-EBUSY ? -EINVAL ?
> +#define MSS_SYS_MAILBOX_DATA_OFFSET 0u
> +
> +/***************SCBCTRL SERVICES_CR register*************************/
I personally prefer more sober comments :)
May be drop the "*********************" ?
> +
> +#define SCBCTRL_SERVICESCR_REQ (0u)
> +#define SCBCTRL_SERVICESCR_REQ_MASK BIT(SCBCTRL_SERVICESCR_REQ)
> +
> +#define SCBCTRL_SERVICESCR_BUSY (1u)
> +#define SCBCTRL_SERVICESCR_BUSY_MASK BIT(SCBCTRL_SERVICESCR_BUSY)
> +
> +#define SCBCTRL_SERVICESCR_ABORT (2u)
> +#define SCBCTRL_SERVICESCR_ABORT_MASK BIT(SCBCTRL_SERVICESCR_ABORT)
> +
> +#define SCBCTRL_SERVICESCR_NOTIFY (3u)
> +#define SCBCTRL_SERVICESCR_NOTIFY_MASK BIT(SCBCTRL_SERVICESCR_NOTIFY)
> +
> +#define SCBCTRL_SERVICESCR_COMMAND (16u)
> +#define SCBCTRL_SERVICESCR_COMMAND_MASK (0xffffu << SCBCTRL_SERVICESCR_COMMAND)
If you use BIT(), then it would be better to use GENMASK() here.
> +
> +/***************SCBCTRL SERVICES_SR registers*************************/
> +
> +#define SCBCTRL_SERVICESSR_REQ (0u)
> +#define SCBCTRL_SERVICESSR_REQ_MASK BIT(SCBCTRL_SERVICESSR_REQ)
> +
> +#define SCBCTRL_SERVICESSR_BUSY (1u)
> +#define SCBCTRL_SERVICESSR_BUSY_MASK BIT(SCBCTRL_SERVICESSR_BUSY)
> +
> +#define SCBCTRL_SERVICESSR_ABORT (2u)
> +#define SCBCTRL_SERVICESSR_ABORT_MASK BIT(SCBCTRL_SERVICESSR_ABORT)
> +
> +#define SCBCTRL_SERVICESSR_NOTIFY (3u)
> +#define SCBCTRL_SERVICESSR_NOTIFY_MASK BIT(SCBCTRL_SERVICESSR_NOTIFY)
> +
> +#define SCBCTRL_SERVICESSR_STATUS (16u)
> +#define SCBCTRL_SERVICESSR_STATUS_MASK (0xffffu << SCBCTRL_SERVICESSR_STATUS)
GENMASK().
> +
> +struct mpfs_mbox {
> + struct mbox_controller controller;
> + struct device *dev;
> + int irq;
> + void __iomem *mailbox_base;
> + void __iomem *int_reg;
> + struct mbox_chan *chan;
> + u16 response_size;
> + u16 response_offset;
> +};
> +
> +static int mpfs_mbox_busy(struct mpfs_mbox *mbox)
Return bool ?
> +{
> + u32 status;
> +
> + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET);
> +
> + return status & SCBCTRL_SERVICESSR_BUSY_MASK;
> +}
> +
> +static struct mpfs_mbox *mbox_chan_to_mpfs_mbox(struct mbox_chan *chan)
> +{
> + if (!chan || !chan->con_priv)
> + return NULL;
Is this ever called with chan == NULL ?
> +
> + return (struct mpfs_mbox *)chan->con_priv;
> +}
> +
> +static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
> +{
> + u32 index;
> + u32 *word_buf;
> + u8 *byte_buf;
> + u8 byte_off;
> + u8 byte_index;
> + u32 mailbox_val = 0u;
> + u16 mb_offset;
> + u16 mbox_options_select;
> + u32 mbox_tx_trigger;
> +
> + struct mpfs_mss_msg *msg = data;
> +
> + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
Please remove the empty lines before the declarations.
> +
> + mb_offset = msg->mailbox_offset;
> + mbox->response_size = msg->response_size;
> + mbox->response_offset = msg->response_offset;
> +
> + mbox_options_select = ((mb_offset << 7u) | (msg->cmd_opcode & 0x7fu));
> + mbox_tx_trigger = (((mbox_options_select << SCBCTRL_SERVICESCR_COMMAND) &
> + SCBCTRL_SERVICESCR_COMMAND_MASK) |
> + SCBCTRL_SERVICESCR_REQ_MASK | SCBCTRL_SERVICESSR_NOTIFY_MASK);
> +
> + if (mpfs_mbox_busy(mbox))
> + return MSS_SYS_BUSY;
You can probably move this before the previous hunk, no ? If you are going to do
nothing, then let's detect it earlier.
> +
> + /* Code for MSS_SYS_PARAM_ERR is not implemented with this version of driver. */
> +
> + writel_relaxed(0x0U, mbox->int_reg);
> +
> + if (msg->cmd_data_size > 0u) {
0u ? Seriously ?
> + byte_buf = (u8 *)(msg->cmd_data);
> +
> + for (index = 0u; index < (msg->cmd_data_size / 4u); index++) {
> + writel_relaxed(word_buf[index],
> + mbox->mailbox_base + MAILBOX_REG_OFFSET + index);
> + }
> +
> + if ((msg->cmd_data_size % 4u) > 0u) {
> + byte_off = (((msg->cmd_data_size / 4u) * 4u));
There are in my opinion far too many "u"s... Many of them are not necessary and
just make the code harder to read.
> + byte_buf = (u8 *)(msg->cmd_data + byte_off);
> +
> + mailbox_val = readl_relaxed(mbox->mailbox_base +
> + MAILBOX_REG_OFFSET + index);
> +
> + for (byte_index = 0u;
> + byte_index < (msg->cmd_data_size % 4u);
> + byte_index++) {
s/byte_index/i and your line would become shorter and easier to read.
> + mailbox_val &= ~(0xffu << (byte_index * 8u));
> + mailbox_val |= (byte_buf[byte_index]
> + << (byte_index * 8u));
> + }
> +
> + writel_relaxed(mailbox_val,
> + mbox->mailbox_base + MAILBOX_REG_OFFSET + index);
> + }
> + }
> +
> + writel_relaxed(mbox_tx_trigger, mbox->mailbox_base + SERVICES_CR_OFFSET);
> +
> + return MSS_SYS_SUCCESS;
> +}
> +
> +static inline int mpfs_mbox_pending(struct mpfs_mbox *mbox)
return bool ?
> +{
> + u32 status;
> +
> + status = readl_relaxed(mbox->mailbox_base + SERVICES_SR_OFFSET);
> +
> + return !(status & SCBCTRL_SERVICESSR_BUSY_MASK);
> +}
> +
> +static void mpfs_mbox_rx_data(struct mbox_chan *chan)
> +{
> + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
> + u32 *data;
> + u32 index;
> + u32 response_limit;
> +
> + data = devm_kzalloc(mbox->dev, sizeof(*data) * mbox->response_size,
> + GFP_ATOMIC);
check the result please. What if that fails ? That is a GFP_ATOMIC. It can fail...
> +
> + response_limit = (mbox->response_size) + (mbox->response_offset);
> + if (mpfs_mbox_pending(mbox) && mbox->response_size > 0U) {
> + for (index = (mbox->response_offset); index < response_limit;
> + index++) {
s/index/i
> + data[index - (mbox->response_offset)] =
> + readl_relaxed(mbox->mailbox_base + MAILBOX_REG_OFFSET +
> + index * 0x4);
> + }
> + }
> +
> + mbox_chan_received_data(chan, (void *)data);
> + devm_kfree(mbox->dev, data);
> +}
> +
> +static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
> +{
> + struct mbox_chan *chan = (struct mbox_chan *)data;
> + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
> +
> + writel_relaxed(0x0U, mbox->int_reg);
> +
> + mpfs_mbox_rx_data(chan);
> +
> + mbox_chan_txdone(chan, 0);
> + return IRQ_HANDLED;
> +}
> +
> +static int mpfs_mbox_startup(struct mbox_chan *chan)
> +{
> + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
> + int ret = 0;
> +
> + if (!mbox)
> + return -EINVAL;
> + ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0,
> + "mpfs-mailbox", chan);
> + if (unlikely(ret)) {
I do not think the unlikely is needed here. This is not hot-path.
> + dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n",
> + ret);
> + return ret;
you do not need this return. Or at least change the next return to 0.
> + }
> +
> + return ret;
> +}
> +
> +static void mpfs_mbox_shutdown(struct mbox_chan *chan)
> +{
> + struct mpfs_mbox *mbox = mbox_chan_to_mpfs_mbox(chan);
> +
> + devm_free_irq(mbox->dev, mbox->irq, chan);
> +}
> +
> +static const struct mbox_chan_ops mpfs_mbox_ops = {
> + .send_data = mpfs_mbox_send_data,
> + .startup = mpfs_mbox_startup,
> + .shutdown = mpfs_mbox_shutdown,
> +};
> +
> +static int mpfs_mbox_probe(struct platform_device *pdev)
> +{
> + struct mpfs_mbox *mbox;
> + struct resource *regs;
> + struct mbox_chan *chans;
> + int ret;
> +
> + mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
> + if (!mbox)
> + return -ENOMEM;
> +
> + chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
> + if (!chans)
> + return -ENOMEM;
> +
> + mbox->mailbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
> + if (IS_ERR(mbox->mailbox_base))
> + return PTR_ERR(mbox->mailbox_base);
> +
> + mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s);
> + if (IS_ERR(mbox->int_reg))
> + return PTR_ERR(mbox->int_reg);
> +
> + mbox->irq = platform_get_irq(pdev, 0);
No error check ? Or did you mean to use platform_get_irq_optional() ?
> +
> + mbox->dev = &pdev->dev;
> +
> + chans[0].con_priv = mbox;
> + mbox->controller.dev = mbox->dev;
> + mbox->controller.num_chans = 1;
> + mbox->controller.chans = chans;
> + mbox->controller.ops = &mpfs_mbox_ops;
> + mbox->controller.txdone_irq = true;
> +
> + ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
> + if (ret) {
> + dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
> + return -1;
return ret;
> + }
> + dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mpfs_mbox_of_match[] = {
> + {
> + .compatible = "microchip,polarfire-soc-mailbox",
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
> +
> +static struct platform_driver mpfs_mbox_driver = {
> + .driver = {
> + .name = "mpfs-mailbox",
> + .of_match_table = mpfs_mbox_of_match,
> + },
> + .probe = mpfs_mbox_probe,
> +};
> +module_platform_driver(mpfs_mbox_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
> +MODULE_DESCRIPTION("MPFS mailbox controller driver");
>
--
Damien Le Moal
Western Digital Research
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/6] mbox: add polarfire soc system controller mailbox
2020-11-20 0:05 ` Damien Le Moal
@ 2020-11-30 13:23 ` Conor.Dooley
2020-11-30 21:50 ` Damien Le Moal
0 siblings, 1 reply; 5+ messages in thread
From: Conor.Dooley @ 2020-11-30 13:23 UTC (permalink / raw)
To: Damien.LeMoal, robh+dt, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: Cyril.Jean, david.abdurachmanov, Daire.McNamara, Anup.Patel,
Atish.Patra, Lewis.Hanly
On 20/11/2020 00:05, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> This driver adds support for the single mailbox channel of the MSS
>> system controller on the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> drivers/mailbox/Kconfig | 12 ++
>> drivers/mailbox/Makefile | 2 +
>> drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++
>> 3 files changed, 310 insertions(+)
>> create mode 100644 drivers/mailbox/mailbox-mpfs.c
>>
>> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
>> index 05b1009e2820..4881a519683a 100644
>> --- a/drivers/mailbox/Kconfig
>> +++ b/drivers/mailbox/Kconfig
>> @@ -153,6 +153,18 @@ config MAILBOX_TEST
>> Test client to help with testing new Controller driver
>> implementations.
>>
>> +config MPFS_MBOX
>> + tristate "MPFS Mailbox"
>> + depends on HAS_IOMEM
> Shouldn't this dependency be on SOC_MICROCHIP_POLARFIRE ?
Not entirely sure what you mean by this one. You want the HAS_IOMEM to be selected by SOC_MICROCHIP_POLARFIRE ?
>
>> + depends on SOC_MICROCHIP_POLARFIRE
>> + help
>> + This driver adds support for the Polarfire SoC mailbox controller.
>> +
>> + To compile this driver as a module, choose M here. the
>> + module will be called mailbox-mpfs.
>> +
>> + If unsure, say Y.
>> +
>> config QCOM_APCS_IPC
>> tristate "Qualcomm APCS IPC driver"
>> depends on ARCH_QCOM || COMPILE_TEST
>> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
>> index 2e06e02b2e03..63f49b5bcc43 100644
>> --- a/drivers/mailbox/Makefile
>> +++ b/drivers/mailbox/Makefile
>> @@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
>>
>> obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
>>
>> +obj-$(CONFIG_MPFS_MBOX) += mailbox-mpfs.o
>> +
>> obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
>>
>> obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
>> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
>> new file mode 100644
>> index 000000000000..686ccd3317f9
>> --- /dev/null
>> +++ b/drivers/mailbox/mailbox-mpfs.c
>> @@ -0,0 +1,296 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Microchip MPFS system controller/mailbox controller driver
>> + *
>> + * Copyright (c) 2020 Microchip Corporation. All rights reserved.
>> + *
>> + * Author: Conor Dooley <conor.dooley@microchip.com>
>> + *
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/kernel.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/mailbox_controller.h>
>> +#include <soc/microchip/mpfs.h>
>> +
>> +#define SERVICES_CR_OFFSET 0x50u
>> +#define SERVICES_SR_OFFSET 0x54u
>> +#define MAILBOX_REG_OFFSET 0x800u
>> +#define MSS_SYS_SUCCESS 0u
trimmed, will address the rest in V2
> --
> Damien Le Moal
> Western Digital Research
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/6] mbox: add polarfire soc system controller mailbox
2020-11-30 13:23 ` Conor.Dooley
@ 2020-11-30 21:50 ` Damien Le Moal
2020-12-01 10:11 ` Ben Dooks
0 siblings, 1 reply; 5+ messages in thread
From: Damien Le Moal @ 2020-11-30 21:50 UTC (permalink / raw)
To: Conor.Dooley, robh+dt, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: Cyril.Jean, david.abdurachmanov, Daire.McNamara, Anup Patel,
Atish Patra, Lewis.Hanly
On 2020/11/30 22:23, Conor.Dooley@microchip.com wrote:
> On 20/11/2020 00:05, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> This driver adds support for the single mailbox channel of the MSS
>>> system controller on the Microchip PolarFire SoC.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> drivers/mailbox/Kconfig | 12 ++
>>> drivers/mailbox/Makefile | 2 +
>>> drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++
>>> 3 files changed, 310 insertions(+)
>>> create mode 100644 drivers/mailbox/mailbox-mpfs.c
>>>
>>> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
>>> index 05b1009e2820..4881a519683a 100644
>>> --- a/drivers/mailbox/Kconfig
>>> +++ b/drivers/mailbox/Kconfig
>>> @@ -153,6 +153,18 @@ config MAILBOX_TEST
>>> Test client to help with testing new Controller driver
>>> implementations.
>>>
>>> +config MPFS_MBOX
>>> + tristate "MPFS Mailbox"
>>> + depends on HAS_IOMEM
>> Shouldn't this dependency be on SOC_MICROCHIP_POLARFIRE ?
> Not entirely sure what you mean by this one. You want the HAS_IOMEM to be selected by SOC_MICROCHIP_POLARFIRE ?
Sorry, I was not clear. I was referring to MPFS_MBOX: shouldn't it be dependent
on SOC_MICROCHIP_POLARFIRE ? E.g.:
config MPFS_MBOX
tristate "MPFS Mailbox"
depends on HAS_IOMEM
depends on SOC_MICROCHIP_POLARFIRE
...
Since it will probably not make sense to compile the driver when the SoC support
is not selected. No ?
>>
>>> + depends on SOC_MICROCHIP_POLARFIRE
>>> + help
>>> + This driver adds support for the Polarfire SoC mailbox controller.
>>> +
>>> + To compile this driver as a module, choose M here. the
>>> + module will be called mailbox-mpfs.
>>> +
>>> + If unsure, say Y.
>>> +
>>> config QCOM_APCS_IPC
>>> tristate "Qualcomm APCS IPC driver"
>>> depends on ARCH_QCOM || COMPILE_TEST
>>> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
>>> index 2e06e02b2e03..63f49b5bcc43 100644
>>> --- a/drivers/mailbox/Makefile
>>> +++ b/drivers/mailbox/Makefile
>>> @@ -39,6 +39,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
>>>
>>> obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
>>>
>>> +obj-$(CONFIG_MPFS_MBOX) += mailbox-mpfs.o
>>> +
>>> obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
>>>
>>> obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
>>> diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
>>> new file mode 100644
>>> index 000000000000..686ccd3317f9
>>> --- /dev/null
>>> +++ b/drivers/mailbox/mailbox-mpfs.c
>>> @@ -0,0 +1,296 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Microchip MPFS system controller/mailbox controller driver
>>> + *
>>> + * Copyright (c) 2020 Microchip Corporation. All rights reserved.
>>> + *
>>> + * Author: Conor Dooley <conor.dooley@microchip.com>
>>> + *
>>> + */
>>> +
>>> +#include <linux/io.h>
>>> +#include <linux/err.h>
>>> +#include <linux/init.h>
>>> +#include <linux/module.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/mailbox_controller.h>
>>> +#include <soc/microchip/mpfs.h>
>>> +
>>> +#define SERVICES_CR_OFFSET 0x50u
>>> +#define SERVICES_SR_OFFSET 0x54u
>>> +#define MAILBOX_REG_OFFSET 0x800u
>>> +#define MSS_SYS_SUCCESS 0u
> trimmed, will address the rest in V2
>> --
>> Damien Le Moal
>> Western Digital Research
>
>
>
>
--
Damien Le Moal
Western Digital Research
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/6] mbox: add polarfire soc system controller mailbox
2020-11-30 21:50 ` Damien Le Moal
@ 2020-12-01 10:11 ` Ben Dooks
0 siblings, 0 replies; 5+ messages in thread
From: Ben Dooks @ 2020-12-01 10:11 UTC (permalink / raw)
To: Damien Le Moal, Conor.Dooley, robh+dt, jassisinghbrar, aou,
paul.walmsley, palmer, devicetree, linux-riscv
Cc: Cyril.Jean, david.abdurachmanov, Daire.McNamara, Anup Patel,
Atish Patra, Lewis.Hanly
On 30/11/2020 21:50, Damien Le Moal wrote:
> On 2020/11/30 22:23, Conor.Dooley@microchip.com wrote:
>> On 20/11/2020 00:05, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> This driver adds support for the single mailbox channel of the MSS
>>>> system controller on the Microchip PolarFire SoC.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> drivers/mailbox/Kconfig | 12 ++
>>>> drivers/mailbox/Makefile | 2 +
>>>> drivers/mailbox/mailbox-mpfs.c | 296 +++++++++++++++++++++++++++++++++
>>>> 3 files changed, 310 insertions(+)
>>>> create mode 100644 drivers/mailbox/mailbox-mpfs.c
>>>>
>>>> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
>>>> index 05b1009e2820..4881a519683a 100644
>>>> --- a/drivers/mailbox/Kconfig
>>>> +++ b/drivers/mailbox/Kconfig
>>>> @@ -153,6 +153,18 @@ config MAILBOX_TEST
>>>> Test client to help with testing new Controller driver
>>>> implementations.
>>>>
>>>> +config MPFS_MBOX
>>>> + tristate "MPFS Mailbox"
>>>> + depends on HAS_IOMEM
>>> Shouldn't this dependency be on SOC_MICROCHIP_POLARFIRE ?
>> Not entirely sure what you mean by this one. You want the HAS_IOMEM to be selected by SOC_MICROCHIP_POLARFIRE ?
>
> Sorry, I was not clear. I was referring to MPFS_MBOX: shouldn't it be dependent
> on SOC_MICROCHIP_POLARFIRE ? E.g.:
>
> config MPFS_MBOX
> tristate "MPFS Mailbox"
> depends on HAS_IOMEM
> depends on SOC_MICROCHIP_POLARFIRE
> ...
probably depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
so that you can build a "compile test" kernel with as much enabled as
possible
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
https://www.codethink.co.uk/privacy.html
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-12-01 10:25 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-11-19 17:04 [PATCH 1/6] mbox: add polarfire soc system controller mailbox conor.dooley
2020-11-20 0:05 ` Damien Le Moal
2020-11-30 13:23 ` Conor.Dooley
2020-11-30 21:50 ` Damien Le Moal
2020-12-01 10:11 ` Ben Dooks
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