[PATCH v3 0/2] riscv: Dump faulting instructions in oops handler

[PATCH v3 0/2] riscv: Dump faulting instructions in oops handler

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

RISC-V does not dump faulting instructions in the oops handler. This
series adds "Code:" dumps to the oops output together with
scripts/decodecode support.

Thanks,
Björn

v2->v3: Simplifications/getting rid of casts (Geert)
v1->v2: Dump instructions in 16b parcels (Andreas)

Björn Töpel (2):
  riscv: Add instruction dump to RISC-V splats
  scripts/decodecode: Add support for RISC-V

 arch/riscv/kernel/traps.c | 25 ++++++++++++++++++++++++-
 scripts/decodecode        | 12 +++++++++++-
 2 files changed, 35 insertions(+), 2 deletions(-)


base-commit: 7287904c8771b77b9504f53623bb477065c19a58
-- 
2.37.2


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[PATCH v3 1/2] riscv: Add instruction dump to RISC-V splats

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

Add instruction dump (Code:) output to RISC-V splats. Dump 16b
parcels.

An example:
  Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
  Oops [#1]
  Modules linked in:
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.2.0-rc3-00302-g840ff44c571d-dirty #27
  Hardware name: riscv-virtio,qemu (DT)
  epc : kernel_init+0xc8/0x10e
   ra : kernel_init+0x70/0x10e
  epc : ffffffff80bd9a40 ra : ffffffff80bd99e8 sp : ff2000000060bec0
   gp : ffffffff81730b28 tp : ff6000007ff00000 t0 : 7974697275636573
   t1 : 0000000000000000 t2 : 3030303270393d6e s0 : ff2000000060bee0
   s1 : ffffffff81732028 a0 : 0000000000000000 a1 : ff60000080dd1780
   a2 : 0000000000000002 a3 : ffffffff8176a470 a4 : 0000000000000000
   a5 : 000000000000000a a6 : 0000000000000081 a7 : ff60000080dd1780
   s2 : 0000000000000000 s3 : 0000000000000000 s4 : 0000000000000000
   s5 : 0000000000000000 s6 : 0000000000000000 s7 : 0000000000000000
   s8 : 0000000000000000 s9 : 0000000000000000 s10: 0000000000000000
   s11: 0000000000000000 t3 : ffffffff81186018 t4 : 0000000000000022
   t5 : 000000000000003d t6 : 0000000000000000
  status: 0000000200000120 badaddr: 0000000000000000 cause: 000000000000000f
  [<ffffffff80003528>] ret_from_exception+0x0/0x16
  Code: 862a d179 608c a517 0069 0513 2be5 d0ef db2e 47a9 (c11c) a517
  ---[ end trace 0000000000000000 ]---
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
  SMP: stopping secondary CPUs
  ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]---

Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
---
 arch/riscv/kernel/traps.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 549bde5c970a..fbdcdbc792d3 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -29,6 +29,27 @@ int show_unhandled_signals = 1;
 
 static DEFINE_SPINLOCK(die_lock);
 
+static void dump_kernel_instr(const char *loglvl, struct pt_regs *regs)
+{
+	char str[sizeof("0000 ") * 12 + 2 + 1], *p = str;
+	const u16 *insns = (u16 *)instruction_pointer(regs);
+	long bad;
+	u16 val;
+	int i;
+
+	for (i = -10; i < 2; i++) {
+		bad = get_kernel_nofault(val, &insns[i]);
+		if (!bad) {
+			p += sprintf(p, i == 0 ? "(%04hx) " : "%04hx ", val);
+		} else {
+			printk("%sCode: Unable to access instruction at 0x%px.\n",
+			       loglvl, &insns[i]);
+			return;
+		}
+	}
+	printk("%sCode: %s\n", loglvl, str);
+}
+
 void die(struct pt_regs *regs, const char *str)
 {
 	static int die_counter;
@@ -43,8 +64,10 @@ void die(struct pt_regs *regs, const char *str)
 
 	pr_emerg("%s [#%d]\n", str, ++die_counter);
 	print_modules();
-	if (regs)
+	if (regs) {
 		show_regs(regs);
+		dump_kernel_instr(KERN_EMERG, regs);
+	}
 
 	cause = regs ? regs->cause : -1;
 	ret = notify_die(DIE_OOPS, str, regs, 0, cause, SIGSEGV);
-- 
2.37.2


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[PATCH v3 2/2] scripts/decodecode: Add support for RISC-V

[Björn Töpel]

From: Björn Töpel <bjorn@rivosinc.com>

RISC-V has some GNU disassembly quirks, e.g. it requires '-D' to
properly disassemble .2byte directives similar to Arm [1]. Further,
GNU objdump groups RISC-V instruction by 2 or 4 byte chunks, instead
doing byte-for-byte.

Add the required switches, and translate from short/word to bytes when
ARCH is "riscv".

An example how to invoke decodecode for RISC-V:
  $ echo 'Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7)
  6140' | AFLAGS="-march=rv64imac_zicbom_zihintpause"  \
  ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- ./scripts/decodecode
  Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7) 6140
  All code
  ========
     0:   bf45                    c.j     0xffffffffffffffb0
     2:   1007f793                andi    a5,a5,256
     6:   f7d9                    c.bnez  a5,0xffffffffffffff94
     8:   37af50ef                jal     ra,0xf5382
     c:   d541                    c.beqz  a0,0xffffffffffffff94
     e:   b7d9                    c.j     0xffffffffffffffd4
    10:   00c87097                auipc   ra,0xc87
    14:*  614080e7                jalr    ra,1556(ra) # 0xc87624          <-- trapping instruction

  Code starting with the faulting instruction
  ===========================================
     0:   614080e7                jalr    ra,1556(ra)

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=10263

Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
---
 scripts/decodecode | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/scripts/decodecode b/scripts/decodecode
index b28fd2686561..8fe71c292381 100755
--- a/scripts/decodecode
+++ b/scripts/decodecode
@@ -93,6 +93,11 @@ disas() {
 		${CROSS_COMPILE}strip $t.o
 	fi
 
+	if [ "$ARCH" = "riscv" ]; then
+		OBJDUMPFLAGS="-M no-aliases --section=.text -D"
+		${CROSS_COMPILE}strip $t.o
+	fi
+
 	if [ $pc_sub -ne 0 ]; then
 		if [ $PC ]; then
 			adj_vma=$(( $PC - $pc_sub ))
@@ -126,8 +131,13 @@ get_substr_opcode_bytes_num()
 	do
 		substr+="$opc"
 
+		opcode="$substr"
+		if [ "$ARCH" = "riscv" ]; then
+			opcode=$(echo $opcode | tr ' ' '\n' | tac | tr -d '\n')
+		fi
+
 		# return if opcode bytes do not match @opline anymore
-		if ! echo $opline | grep -q "$substr";
+		if ! echo $opline | grep -q "$opcode";
 		then
 			break
 		fi
-- 
2.37.2


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Re: [PATCH v3 2/2] scripts/decodecode: Add support for RISC-V

[Alexandre Ghiti]

Hi Björn,

On 1/19/23 08:47, Björn Töpel wrote:
> From: Björn Töpel <bjorn@rivosinc.com>
>
> RISC-V has some GNU disassembly quirks, e.g. it requires '-D' to
> properly disassemble .2byte directives similar to Arm [1]. Further,
> GNU objdump groups RISC-V instruction by 2 or 4 byte chunks, instead
> doing byte-for-byte.
>
> Add the required switches, and translate from short/word to bytes when
> ARCH is "riscv".
>
> An example how to invoke decodecode for RISC-V:
>    $ echo 'Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7)
>    6140' | AFLAGS="-march=rv64imac_zicbom_zihintpause"  \
>    ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- ./scripts/decodecode
>    Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7) 6140
>    All code
>    ========
>       0:   bf45                    c.j     0xffffffffffffffb0
>       2:   1007f793                andi    a5,a5,256
>       6:   f7d9                    c.bnez  a5,0xffffffffffffff94
>       8:   37af50ef                jal     ra,0xf5382
>       c:   d541                    c.beqz  a0,0xffffffffffffff94
>       e:   b7d9                    c.j     0xffffffffffffffd4
>      10:   00c87097                auipc   ra,0xc87
>      14:*  614080e7                jalr    ra,1556(ra) # 0xc87624          <-- trapping instruction
>
>    Code starting with the faulting instruction
>    ===========================================
>       0:   614080e7                jalr    ra,1556(ra)
>
> [1] https://sourceware.org/bugzilla/show_bug.cgi?id=10263
>
> Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
> ---
>   scripts/decodecode | 12 +++++++++++-
>   1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/scripts/decodecode b/scripts/decodecode
> index b28fd2686561..8fe71c292381 100755
> --- a/scripts/decodecode
> +++ b/scripts/decodecode
> @@ -93,6 +93,11 @@ disas() {
>   		${CROSS_COMPILE}strip $t.o
>   	fi
>   
> +	if [ "$ARCH" = "riscv" ]; then
> +		OBJDUMPFLAGS="-M no-aliases --section=.text -D"
> +		${CROSS_COMPILE}strip $t.o
> +	fi
> +
>   	if [ $pc_sub -ne 0 ]; then
>   		if [ $PC ]; then
>   			adj_vma=$(( $PC - $pc_sub ))
> @@ -126,8 +131,13 @@ get_substr_opcode_bytes_num()
>   	do
>   		substr+="$opc"
>   
> +		opcode="$substr"
> +		if [ "$ARCH" = "riscv" ]; then
> +			opcode=$(echo $opcode | tr ' ' '\n' | tac | tr -d '\n')
> +		fi
> +
>   		# return if opcode bytes do not match @opline anymore
> -		if ! echo $opline | grep -q "$substr";
> +		if ! echo $opline | grep -q "$opcode";
>   		then
>   			break
>   		fi


Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks, that's very useful!

Alex


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Re: [PATCH v3 0/2] riscv: Dump faulting instructions in oops handler

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Thu, 19 Jan 2023 08:47:36 +0100 you wrote:
> From: Björn Töpel <bjorn@rivosinc.com>
> 
> RISC-V does not dump faulting instructions in the oops handler. This
> series adds "Code:" dumps to the oops output together with
> scripts/decodecode support.
> 
> Thanks,
> Björn
> 
> [...]

Here is the summary with links:
  - [v3,1/2] riscv: Add instruction dump to RISC-V splats
    https://git.kernel.org/riscv/c/eb165bfa8eaf
  - [v3,2/2] scripts/decodecode: Add support for RISC-V
    https://git.kernel.org/riscv/c/00b242509c8f

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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