From: Palmer Dabbelt <palmer@dabbelt.com>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: aou@eecs.berkeley.edu, Anup Patel <Anup.Patel@wdc.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Atish Patra <Atish.Patra@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
mick@ics.forth.gr, akpm@linux-foundation.org, ardb@kernel.org,
rppt@kernel.org
Subject: Re: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32
Date: Wed, 13 Jan 2021 21:09:34 -0800 (PST) [thread overview]
Message-ID: <mhng-1400a3dd-651b-4a78-bb2d-1f10580add75@palmerdabbelt-glaptop> (raw)
In-Reply-To: <20210107092652.3438696-4-atish.patra@wdc.com>
On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
> SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
> 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
> allocation if it is requested to be aligned with SMP_CACHE_BYTES.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> arch/riscv/include/asm/cache.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index 9b58b104559e..c9c669ea2fe6 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -7,7 +7,11 @@
> #ifndef _ASM_RISCV_CACHE_H
> #define _ASM_RISCV_CACHE_H
>
> +#ifdef CONFIG_64BIT
> #define L1_CACHE_SHIFT 6
> +#else
> +#define L1_CACHE_SHIFT 5
> +#endif
>
> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
Should we not instead just
#define SMP_CACHE_BYTES L1_CACHE_BYTES
like a handful of architectures do?
The cache size is sort of fake here, as we don't have any non-coherent
mechanisms, but IIRC we wrote somewhere that it's recommended to have 64-byte
cache lines in RISC-V implementations as software may assume that for
performance reasons. Not really a strong reason, but I'd prefer to just make
these match.
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next prev parent reply other threads:[~2021-01-14 5:09 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-07 9:26 [PATCH 0/4] Assorted fixes for RV32 Atish Patra
2021-01-07 9:26 ` [PATCH 1/4] RISC-V: Do not allocate memblock while iterating reserved memblocks Atish Patra
2021-01-08 16:25 ` Geert Uytterhoeven
2021-01-11 3:54 ` Anup Patel
2021-01-07 9:26 ` [PATCH 2/4] RISC-V: Set current memblock limit Atish Patra
2021-01-11 3:58 ` Anup Patel
2021-01-11 19:20 ` Atish Patra
2021-01-07 9:26 ` [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 Atish Patra
2021-01-08 16:26 ` Geert Uytterhoeven
2021-01-11 4:00 ` Anup Patel
2021-01-14 5:09 ` Palmer Dabbelt [this message]
2021-01-14 18:33 ` Atish Patra
2021-01-14 19:46 ` Palmer Dabbelt
2021-01-14 21:11 ` Atish Patra
2021-01-14 21:24 ` Palmer Dabbelt
2021-01-15 7:59 ` Geert Uytterhoeven
2021-01-15 22:44 ` Palmer Dabbelt
2021-01-17 19:03 ` Geert Uytterhoeven
2021-01-20 10:59 ` Geert Uytterhoeven
2021-01-16 1:39 ` Atish Patra
2021-01-17 18:55 ` Geert Uytterhoeven
2021-03-12 15:52 ` Geert Uytterhoeven
2021-01-07 9:26 ` [PATCH 4/4] RISC-V: Fix maximum allowed phsyical memory " Atish Patra
2021-01-11 4:04 ` Anup Patel
2021-01-11 4:05 ` [PATCH 0/4] Assorted fixes " Anup Patel
2021-01-14 5:09 ` Palmer Dabbelt
2021-01-14 5:12 ` Palmer Dabbelt
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