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From: Palmer Dabbelt <palmerdabbelt@google.com>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: aou@eecs.berkeley.edu, alexios.zavras@intel.com,
	anup@brainfault.org, linux-kernel@vger.kernel.org,
	rppt@linux.ibm.com, Atish Patra <Atish.Patra@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org, tglx@linutronix.de,
	han_mao@c-sky.com
Subject: Re: [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI.
Date: Mon, 02 Dec 2019 15:59:45 -0800 (PST)
Message-ID: <mhng-18ffe96a-7a03-475f-ae9b-2d450fc3d29e@palmerdabbelt.mtv.corp.google.com> (raw)
In-Reply-To: <20191126190503.19303-2-atish.patra@wdc.com>

On Tue, 26 Nov 2019 11:05:00 PST (-0800), Atish Patra wrote:
> As per the new SBI specification, current SBI implementation version
> is defined as 0.1 and will be removed/replaced in future. Each of the
> function call in 0.1 is defined as a separate extension which makes
> easier to replace them one at a time.
>
> Rename existing implementation to reflect that. This patch is just
> a preparatory patch for SBI v0.2 and doesn't introduce any functional
> changes.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
>  arch/riscv/include/asm/sbi.h | 43 +++++++++++++++++++-----------------
>  1 file changed, 23 insertions(+), 20 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 2570c1e683d3..96aaee270ded 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -9,17 +9,17 @@
>  #include <linux/types.h>
>
>  #ifdef CONFIG_RISCV_SBI
> -#define SBI_SET_TIMER 0
> -#define SBI_CONSOLE_PUTCHAR 1
> -#define SBI_CONSOLE_GETCHAR 2
> -#define SBI_CLEAR_IPI 3
> -#define SBI_SEND_IPI 4
> -#define SBI_REMOTE_FENCE_I 5
> -#define SBI_REMOTE_SFENCE_VMA 6
> -#define SBI_REMOTE_SFENCE_VMA_ASID 7
> -#define SBI_SHUTDOWN 8
> +#define SBI_EXT_0_1_SET_TIMER 0x0
> +#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
> +#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
> +#define SBI_EXT_0_1_CLEAR_IPI 0x3
> +#define SBI_EXT_0_1_SEND_IPI 0x4
> +#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
> +#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
> +#define SBI_EXT_0_1_SHUTDOWN 0x8
>
> -#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
> +#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({             \
>  	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
>  	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);	\
>  	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);	\
> @@ -43,48 +43,50 @@
>
>  static inline void sbi_console_putchar(int ch)
>  {
> -	SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
> +	SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
>  }
>
>  static inline int sbi_console_getchar(void)
>  {
> -	return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
> +	return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
>  }
>
>  static inline void sbi_set_timer(uint64_t stime_value)
>  {
>  #if __riscv_xlen == 32
> -	SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
> +	SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value,
> +			  stime_value >> 32);
>  #else
> -	SBI_CALL_1(SBI_SET_TIMER, stime_value);
> +	SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
>  #endif
>  }
>
>  static inline void sbi_shutdown(void)
>  {
> -	SBI_CALL_0(SBI_SHUTDOWN);
> +	SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
>  }
>
>  static inline void sbi_clear_ipi(void)
>  {
> -	SBI_CALL_0(SBI_CLEAR_IPI);
> +	SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
>  }
>
>  static inline void sbi_send_ipi(const unsigned long *hart_mask)
>  {
> -	SBI_CALL_1(SBI_SEND_IPI, hart_mask);
> +	SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
>  }
>
>  static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
>  {
> -	SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
> +	SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
>  }
>
>  static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>  					 unsigned long start,
>  					 unsigned long size)
>  {
> -	SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
> +	SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask,
> +			  start, size);
>  }
>
>  static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> @@ -92,7 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
>  					      unsigned long size,
>  					      unsigned long asid)
>  {
> -	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> +	SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
> +			  start, size, asid);
>  }
>  #else /* CONFIG_RISCV_SBI */
>  /* stubs for code that is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

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Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-26 19:04 [PATCH v5 0/4] Add support for SBI v0.2 Atish Patra
2019-11-26 19:05 ` [PATCH v5 1/4] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2019-12-02 23:59   ` Palmer Dabbelt [this message]
2019-11-26 19:05 ` [PATCH v5 2/4] RISC-V: Add basic support for SBI v0.2 Atish Patra
2019-12-03 21:17   ` Palmer Dabbelt
2019-11-26 19:05 ` [PATCH v5 3/4] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
2019-12-04 18:52   ` Palmer Dabbelt
2019-12-04 22:03     ` Atish Patra
2019-11-26 19:05 ` [PATCH v5 4/4] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2019-11-29  4:51   ` Anup Patel
2019-11-29  4:57     ` Anup Patel
2019-12-04 21:10       ` Atish Patra
2019-12-04 18:52   ` Palmer Dabbelt
2019-12-04 22:04     ` Atish Patra
2019-12-04 18:56 ` [PATCH v5 0/4] Add support for SBI v0.2 Palmer Dabbelt

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