Re: Random memory corruption with v5.2

From: Palmer Dabbelt <palmer@sifive.com>
To: schwab@suse.de
Cc: linux-riscv@lists.infradead.org, david.abdurachmanov@gmail.com,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: Random memory corruption with v5.2
Date: Thu, 01 Aug 2019 12:57:01 -0700 (PDT)	[thread overview]
Message-ID: <mhng-35379643-72bf-48a5-bd5f-be8a5becf87f@palmer-si-x1e> (raw)
In-Reply-To: <mvmo91a8xgh.fsf@suse.de>

On Wed, 31 Jul 2019 00:39:10 PDT (-0700), schwab@suse.de wrote:
> On Jul 30 2019, Paul Walmsley <paul.walmsley@sifive.com> wrote:
>
>> - Commit bf587caae305ae3b4393077fb22c98478ee55755 ("riscv: mm: synchronize
>> MMU after pte change")
>
> That would be my favorite.

If that patch causes memory corruption then something scary is going on.  I
haven't been following the thread closely enough to know how easy this is to
reproduce, but do you mind trying a kernel with a reverted version of that
commit?

This is also availiable on the "for-andreas" branch of git.kernel.org/palmer/linux.git

    commit 07d45256aa8641057c141f1a661bb29dd99eb32e
    gpg: Signature made Thu 01 Aug 2019 12:46:22 PM PDT
    gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
    gpg:                issuer "palmer@dabbelt.com"
    gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [ultimate]
    gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [ultimate]
    Author: Palmer Dabbelt <palmer@sifive.com>
    Date:   Thu Aug 1 12:45:12 2019 -0700

        Revert "riscv: mm: synchronize MMU after pte change"

        Andreas Schwab is seeing some random memory corruption with 5.2, and he
        thinks the reverted comit is the most likely candidate.  The commit
        itself doesn't revert cleanly, but that's just because getting the
        comment right took two commits.

        If this does fix the issue then we're in a bit of trouble, as this TLB
        flush should be pretty safe.

        This reverts commit bf587caae305ae3b4393077fb22c98478ee55755.

        Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

    diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
    index f960c3f4ce47..28dccb072255 100644
    --- a/arch/riscv/mm/fault.c
    +++ b/arch/riscv/mm/fault.c
    @@ -16,7 +16,6 @@

     #include <asm/pgalloc.h>
     #include <asm/ptrace.h>
    -#include <asm/tlbflush.h>

     /*
      * This routine handles page faults.  It determines the address and the
    @@ -267,14 +266,6 @@ asmlinkage void do_page_fault(struct pt_regs *regs)
                    if (!pte_present(*pte_k))
                            goto no_context;

    -               /*
    -                * The kernel assumes that TLBs don't cache invalid
    -                * entries, but in RISC-V, SFENCE.VMA specifies an
    -                * ordering constraint, not a cache flush; it is
    -                * necessary even after writing invalid entries.
    -                */
    -               local_flush_tlb_page(addr);
    -
                    return;
            }
     }

>> - Commit 6dd91e0eacff0a5c822ca37565d6b5740c4d2a80 ("RISC-V: defconfig:
>> Enable NO_HZ_IDLE and HIGH_RES_TIMERS")
>
> I had these enabled forever already.

IIRC that was the argument for enabling them in defconfig :)

>> - Commit 671f9a3e2e24cdeb2d2856abee7422f093e23e29 ("RISC-V: Setup initial
>> page tables in two stages")
>
> I don't think a one-time initial setup can have such a subtle effect.

As per Anup, it's not in 5.2.

>
> Andreas.

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