* [PATCH] RISC-V: recognize S/U mode bits in print_isa @ 2018-11-09 19:33 Patrick Stählin 2018-11-09 19:33 ` Patrick Stählin 2018-11-09 21:07 ` Palmer Dabbelt 0 siblings, 2 replies; 8+ messages in thread From: Patrick Stählin @ 2018-11-09 19:33 UTC (permalink / raw) To: linux-riscv Removes the warning about an unsupported ISA when reading /proc/cpuinfo on QEMU. Signed-off-by: Patrick St?hlin <me@packi.ch> --- arch/riscv/kernel/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3a5a2ee31547..4029c7e6872b 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) static void print_isa(struct seq_file *f, const char *orig_isa) { - static const char *ext = "mafdc"; + static const char *ext = "mafdcsu"; const char *isa = orig_isa; const char *e; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 19:33 [PATCH] RISC-V: recognize S/U mode bits in print_isa Patrick Stählin @ 2018-11-09 19:33 ` Patrick Stählin 2018-11-09 21:07 ` Palmer Dabbelt 1 sibling, 0 replies; 8+ messages in thread From: Patrick Stählin @ 2018-11-09 19:33 UTC (permalink / raw) To: linux-riscv Cc: Patrick Stählin, Albert Ou, Anup Patel, Palmer Dabbelt, linux-kernel, Atish Patra Removes the warning about an unsupported ISA when reading /proc/cpuinfo on QEMU. Signed-off-by: Patrick Stählin <me@packi.ch> --- arch/riscv/kernel/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3a5a2ee31547..4029c7e6872b 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) static void print_isa(struct seq_file *f, const char *orig_isa) { - static const char *ext = "mafdc"; + static const char *ext = "mafdcsu"; const char *isa = orig_isa; const char *e; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 19:33 [PATCH] RISC-V: recognize S/U mode bits in print_isa Patrick Stählin 2018-11-09 19:33 ` Patrick Stählin @ 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:42 ` [PATCH v2] " Patrick Stählin 1 sibling, 2 replies; 8+ messages in thread From: Palmer Dabbelt @ 2018-11-09 21:07 UTC (permalink / raw) To: linux-riscv On Fri, 09 Nov 2018 11:33:47 PST (-0800), me at packi.ch wrote: > Removes the warning about an unsupported ISA when reading /proc/cpuinfo > on QEMU. > > Signed-off-by: Patrick St?hlin <me@packi.ch> > --- > arch/riscv/kernel/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 3a5a2ee31547..4029c7e6872b 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) > > static void print_isa(struct seq_file *f, const char *orig_isa) > { > - static const char *ext = "mafdc"; > + static const char *ext = "mafdcsu"; > const char *isa = orig_isa; > const char *e; This is a bit pedantic, but the "S" extension should really be hidden from userspace. ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 21:07 ` Palmer Dabbelt @ 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:42 ` [PATCH v2] " Patrick Stählin 1 sibling, 0 replies; 8+ messages in thread From: Palmer Dabbelt @ 2018-11-09 21:07 UTC (permalink / raw) To: me; +Cc: me, aou, anup, linux-kernel, atish.patra, linux-riscv On Fri, 09 Nov 2018 11:33:47 PST (-0800), me@packi.ch wrote: > Removes the warning about an unsupported ISA when reading /proc/cpuinfo > on QEMU. > > Signed-off-by: Patrick Stählin <me@packi.ch> > --- > arch/riscv/kernel/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 3a5a2ee31547..4029c7e6872b 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) > > static void print_isa(struct seq_file *f, const char *orig_isa) > { > - static const char *ext = "mafdc"; > + static const char *ext = "mafdcsu"; > const char *isa = orig_isa; > const char *e; This is a bit pedantic, but the "S" extension should really be hidden from userspace. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:07 ` Palmer Dabbelt @ 2018-11-09 21:42 ` Patrick Stählin 2018-11-09 21:42 ` Patrick Stählin 2018-11-16 16:52 ` Palmer Dabbelt 1 sibling, 2 replies; 8+ messages in thread From: Patrick Stählin @ 2018-11-09 21:42 UTC (permalink / raw) To: linux-riscv Removes the warning about an unsupported ISA when reading /proc/cpuinfo on QEMU. The "S" extension is not being returned as it is not accessible from userspace. Signed-off-by: Patrick St?hlin <me@packi.ch> --- arch/riscv/kernel/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3a5a2ee31547..b4a7d4427fbb 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) static void print_isa(struct seq_file *f, const char *orig_isa) { - static const char *ext = "mafdc"; + static const char *ext = "mafdcsu"; const char *isa = orig_isa; const char *e; @@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa) /* * Check the rest of the ISA string for valid extensions, printing those * we find. RISC-V ISA strings define an order, so we only print the - * extension bits when they're in order. + * extension bits when they're in order. Hide the supervisor (S) + * extension from userspace as it's not accessible from there. */ for (e = ext; *e != '\0'; ++e) { if (isa[0] == e[0]) { - seq_write(f, isa, 1); + if (isa[0] != 's') + seq_write(f, isa, 1); + isa++; } } -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 21:42 ` [PATCH v2] " Patrick Stählin @ 2018-11-09 21:42 ` Patrick Stählin 2018-11-16 16:52 ` Palmer Dabbelt 1 sibling, 0 replies; 8+ messages in thread From: Patrick Stählin @ 2018-11-09 21:42 UTC (permalink / raw) To: linux-riscv Cc: Patrick Stählin, Albert Ou, Anup Patel, Palmer Dabbelt, linux-kernel, Atish Patra Removes the warning about an unsupported ISA when reading /proc/cpuinfo on QEMU. The "S" extension is not being returned as it is not accessible from userspace. Signed-off-by: Patrick Stählin <me@packi.ch> --- arch/riscv/kernel/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 3a5a2ee31547..b4a7d4427fbb 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) static void print_isa(struct seq_file *f, const char *orig_isa) { - static const char *ext = "mafdc"; + static const char *ext = "mafdcsu"; const char *isa = orig_isa; const char *e; @@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa) /* * Check the rest of the ISA string for valid extensions, printing those * we find. RISC-V ISA strings define an order, so we only print the - * extension bits when they're in order. + * extension bits when they're in order. Hide the supervisor (S) + * extension from userspace as it's not accessible from there. */ for (e = ext; *e != '\0'; ++e) { if (isa[0] == e[0]) { - seq_write(f, isa, 1); + if (isa[0] != 's') + seq_write(f, isa, 1); + isa++; } } -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2] RISC-V: recognize S/U mode bits in print_isa 2018-11-09 21:42 ` [PATCH v2] " Patrick Stählin 2018-11-09 21:42 ` Patrick Stählin @ 2018-11-16 16:52 ` Palmer Dabbelt 2018-11-16 16:52 ` Palmer Dabbelt 1 sibling, 1 reply; 8+ messages in thread From: Palmer Dabbelt @ 2018-11-16 16:52 UTC (permalink / raw) To: linux-riscv On Fri, 09 Nov 2018 13:42:16 PST (-0800), me at packi.ch wrote: > Removes the warning about an unsupported ISA when reading /proc/cpuinfo > on QEMU. The "S" extension is not being returned as it is not accessible > from userspace. > > Signed-off-by: Patrick St?hlin <me@packi.ch> > --- > arch/riscv/kernel/cpu.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 3a5a2ee31547..b4a7d4427fbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) > > static void print_isa(struct seq_file *f, const char *orig_isa) > { > - static const char *ext = "mafdc"; > + static const char *ext = "mafdcsu"; > const char *isa = orig_isa; > const char *e; > > @@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa) > /* > * Check the rest of the ISA string for valid extensions, printing those > * we find. RISC-V ISA strings define an order, so we only print the > - * extension bits when they're in order. > + * extension bits when they're in order. Hide the supervisor (S) > + * extension from userspace as it's not accessible from there. > */ > for (e = ext; *e != '\0'; ++e) { > if (isa[0] == e[0]) { > - seq_write(f, isa, 1); > + if (isa[0] != 's') > + seq_write(f, isa, 1); > + > isa++; > } > } This looks good to me. I'll target it for the RCs, as it's fairly small and that warning fires too often. Thanks! ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] RISC-V: recognize S/U mode bits in print_isa 2018-11-16 16:52 ` Palmer Dabbelt @ 2018-11-16 16:52 ` Palmer Dabbelt 0 siblings, 0 replies; 8+ messages in thread From: Palmer Dabbelt @ 2018-11-16 16:52 UTC (permalink / raw) To: me; +Cc: me, aou, anup, linux-kernel, atish.patra, linux-riscv On Fri, 09 Nov 2018 13:42:16 PST (-0800), me@packi.ch wrote: > Removes the warning about an unsupported ISA when reading /proc/cpuinfo > on QEMU. The "S" extension is not being returned as it is not accessible > from userspace. > > Signed-off-by: Patrick Stählin <me@packi.ch> > --- > arch/riscv/kernel/cpu.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 3a5a2ee31547..b4a7d4427fbb 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node) > > static void print_isa(struct seq_file *f, const char *orig_isa) > { > - static const char *ext = "mafdc"; > + static const char *ext = "mafdcsu"; > const char *isa = orig_isa; > const char *e; > > @@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa) > /* > * Check the rest of the ISA string for valid extensions, printing those > * we find. RISC-V ISA strings define an order, so we only print the > - * extension bits when they're in order. > + * extension bits when they're in order. Hide the supervisor (S) > + * extension from userspace as it's not accessible from there. > */ > for (e = ext; *e != '\0'; ++e) { > if (isa[0] == e[0]) { > - seq_write(f, isa, 1); > + if (isa[0] != 's') > + seq_write(f, isa, 1); > + > isa++; > } > } This looks good to me. I'll target it for the RCs, as it's fairly small and that warning fires too often. Thanks! _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-11-16 16:52 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-09 19:33 [PATCH] RISC-V: recognize S/U mode bits in print_isa Patrick Stählin 2018-11-09 19:33 ` Patrick Stählin 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:07 ` Palmer Dabbelt 2018-11-09 21:42 ` [PATCH v2] " Patrick Stählin 2018-11-09 21:42 ` Patrick Stählin 2018-11-16 16:52 ` Palmer Dabbelt 2018-11-16 16:52 ` Palmer Dabbelt
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