* [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
@ 2020-09-14 2:22 ` Elaine Zhang
2020-09-15 0:41 ` Stephen Boyd
2020-09-14 2:22 ` [PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Elaine Zhang
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:22 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-half-divider.c | 18 ++++----
drivers/clk/rockchip/clk.c | 61 ++++++++++++-------------
2 files changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
div_ops = &clk_half_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- mux ? &mux->hw : NULL, mux_ops,
- div ? &div->hw : NULL, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags);
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw))
+ goto err_div;
- return clk;
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
kfree(mux);
- return ERR_PTR(-ENOMEM);
+ return ERR_CAST(hw);
}
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..46409972983e 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
u8 gate_shift, u8 gate_flags, unsigned long flags,
spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_mux *mux = NULL;
struct clk_gate *gate = NULL;
struct clk_divider *div = NULL;
@@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name,
: &clk_divider_ops;
}
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- mux ? &mux->hw : NULL, mux_ops,
- div ? &div->hw : NULL, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags);
-
- if (IS_ERR(clk)) {
- ret = PTR_ERR(clk);
- goto err_composite;
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags);
+ if (IS_ERR(hw)) {
+ kfree(div);
+ kfree(gate);
+ return ERR_CAST(hw);
}
- return clk;
-err_composite:
- kfree(div);
+ return hw->clk;
err_div:
kfree(gate);
err_gate:
@@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
unsigned long flags, struct rockchip_clk_branch *child,
spinlock_t *lock)
{
+ struct clk_hw *hw;
struct rockchip_clk_frac *frac;
- struct clk *clk;
struct clk_gate *gate = NULL;
struct clk_fractional_divider *div = NULL;
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
div->approximation = rockchip_fractional_approximation;
div_ops = &clk_fractional_divider_ops;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- NULL, NULL,
- &div->hw, div_ops,
- gate ? &gate->hw : NULL, gate_ops,
- flags | CLK_SET_RATE_UNGATE);
- if (IS_ERR(clk)) {
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ &div->hw, div_ops,
+ gate ? &gate->hw : NULL, gate_ops,
+ flags | CLK_SET_RATE_UNGATE);
+ if (IS_ERR(hw)) {
kfree(frac);
- return clk;
+ return ERR_CAST(hw);
}
if (child) {
@@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch(
mux_clk = clk_register(NULL, &frac_mux->hw);
if (IS_ERR(mux_clk)) {
kfree(frac);
- return clk;
+ return mux_clk;
}
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
@@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch(
if (frac->mux_frac_idx >= 0) {
pr_debug("%s: found fractional parent in mux at pos %d\n",
__func__, frac->mux_frac_idx);
- ret = clk_notifier_register(clk, &frac->clk_nb);
+ ret = clk_notifier_register(hw->clk, &frac->clk_nb);
if (ret)
pr_err("%s: failed to register clock notifier for %s\n",
__func__, name);
@@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch(
}
}
- return clk;
+ return hw->clk;
}
static struct clk *rockchip_clk_register_factor_branch(const char *name,
@@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
int gate_offset, u8 gate_shift, u8 gate_flags,
unsigned long flags, spinlock_t *lock)
{
- struct clk *clk;
+ struct clk_hw *hw;
struct clk_gate *gate = NULL;
struct clk_fixed_factor *fix = NULL;
@@ -349,16 +347,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
fix->mult = mult;
fix->div = div;
- clk = clk_register_composite(NULL, name, parent_names, num_parents,
- NULL, NULL,
- &fix->hw, &clk_fixed_factor_ops,
- &gate->hw, &clk_gate_ops, flags);
- if (IS_ERR(clk)) {
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL,
+ &fix->hw, &clk_fixed_factor_ops,
+ &gate->hw, &clk_gate_ops, flags);
+ if (IS_ERR(hw)) {
kfree(fix);
kfree(gate);
+ return ERR_CAST(hw);
}
- return clk;
+ return hw->clk;
}
struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
2020-09-14 2:22 ` [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
@ 2020-09-15 0:41 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:41 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:22:20)
> clk_hw_register_composite it's already exported.
> Preparation for compilation of rK common clock drivers into modules.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reported-by: kernel test robot <lkp@intel.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
2020-09-14 2:22 ` [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
@ 2020-09-14 2:22 ` Elaine Zhang
2020-09-15 0:41 ` Stephen Boyd
2020-09-14 2:22 ` [PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst() Elaine Zhang
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:22 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk-ddr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 9273bce4d7b6..86718c54e56b 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
return clk;
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
2020-09-14 2:22 ` [PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Elaine Zhang
@ 2020-09-15 0:41 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:41 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:22:21)
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module..
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst()
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
2020-09-14 2:22 ` [PATCH v4 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls Elaine Zhang
2020-09-14 2:22 ` [PATCH v4 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() Elaine Zhang
@ 2020-09-14 2:22 ` Elaine Zhang
2020-09-15 0:42 ` Stephen Boyd
2020-09-14 2:22 ` [PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers Elaine Zhang
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:22 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/softrst.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..5d07266745b8 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
.deassert = rockchip_softrst_deassert,
};
-void __init rockchip_register_softrst(struct device_node *np,
- unsigned int num_regs,
- void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+ unsigned int num_regs,
+ void __iomem *base, u8 flags)
{
struct rockchip_softrst *softrst;
int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
kfree(softrst);
}
};
+EXPORT_SYMBOL_GPL(rockchip_register_softrst);
--
2.17.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst()
2020-09-14 2:22 ` [PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst() Elaine Zhang
@ 2020-09-15 0:42 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:42 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:22:22)
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module..
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
` (2 preceding siblings ...)
2020-09-14 2:22 ` [PATCH v4 3/6] clk: rockchip: Export rockchip_register_softrst() Elaine Zhang
@ 2020-09-14 2:22 ` Elaine Zhang
2020-09-15 0:42 ` Stephen Boyd
2020-09-14 2:23 ` [PATCH v4 5/6] clk: rockchip: fix the clk config to support module build Elaine Zhang
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:22 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++----------------
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 46409972983e..b443169dd408 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -360,8 +360,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
return hw->clk;
}
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
- void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base,
+ unsigned long nr_clks)
{
struct rockchip_clk_provider *ctx;
struct clk **clk_table;
@@ -393,14 +394,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
kfree(ctx);
return ERR_PTR(-ENOMEM);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_init);
-void __init rockchip_clk_of_add_provider(struct device_node *np,
- struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
{
if (of_clk_add_provider(np, of_clk_src_onecell_get,
&ctx->clk_data))
pr_err("%s: could not register clk provider\n", __func__);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
struct clk *clk, unsigned int id)
@@ -408,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
if (ctx->clk_data.clks && id)
ctx->clk_data.clks[id] = clk;
}
+EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
struct rockchip_pll_clock *list,
unsigned int nr_pll, int grf_lock_offset)
{
@@ -432,11 +436,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
-void __init rockchip_clk_register_branches(
- struct rockchip_clk_provider *ctx,
- struct rockchip_clk_branch *list,
- unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
{
struct clk *clk = NULL;
unsigned int idx;
@@ -565,14 +569,15 @@ void __init rockchip_clk_register_branches(
rockchip_clk_add_lookup(ctx, clk, list->id);
}
}
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
- unsigned int lookup_id,
- const char *name, const char *const *parent_names,
- u8 num_parents,
- const struct rockchip_cpuclk_reg_data *reg_data,
- const struct rockchip_cpuclk_rate_table *rates,
- int nrates)
+EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const *parent_names,
+ u8 num_parents,
+ const struct rockchip_cpuclk_reg_data *reg_data,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates)
{
struct clk *clk;
@@ -587,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
rockchip_clk_add_lookup(ctx, clk, lookup_id);
}
+EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
-void __init rockchip_clk_protect_critical(const char *const clocks[],
- int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+ int nclocks)
{
int i;
@@ -601,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
clk_prepare_enable(clk);
}
}
+EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
static void __iomem *rst_base;
static unsigned int reg_restart;
@@ -620,10 +627,10 @@ static struct notifier_block rockchip_restart_handler = {
.priority = 128,
};
-void __init
+void
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
- unsigned int reg,
- void (*cb)(void))
+ unsigned int reg,
+ void (*cb)(void))
{
int ret;
@@ -635,3 +642,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
pr_err("%s: cannot register restart handler, %d\n",
__func__, ret);
}
+EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
--
2.17.1
_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers
2020-09-14 2:22 ` [PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers Elaine Zhang
@ 2020-09-15 0:42 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:42 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:22:23)
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 5/6] clk: rockchip: fix the clk config to support module build
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
` (3 preceding siblings ...)
2020-09-14 2:22 ` [PATCH v4 4/6] clk: rockchip: Export some clock common APIs for module drivers Elaine Zhang
@ 2020-09-14 2:23 ` Elaine Zhang
2020-09-15 0:42 ` Stephen Boyd
2020-09-14 2:23 ` [PATCH v4 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
2020-09-22 13:35 ` [PATCH v4 0/6] clk: rockchip: " Heiko Stuebner
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:23 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark CONFIG_CLK_RK3399 to "tristate",
to support building Rk3399 SoC clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/Kconfig | 1 +
drivers/clk/rockchip/Kconfig | 78 +++++++++++++++++++++++++++++++++++
drivers/clk/rockchip/Makefile | 42 ++++++++++---------
3 files changed, 101 insertions(+), 20 deletions(-)
create mode 100644 drivers/clk/rockchip/Kconfig
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac9fac3..b41aaed9bd51 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
source "drivers/clk/sifive/Kconfig"
source "drivers/clk/sprd/Kconfig"
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
new file mode 100644
index 000000000000..a1a21c99d388
--- /dev/null
+++ b/drivers/clk/rockchip/Kconfig
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+# common clock support for ROCKCHIP SoC family.
+
+config COMMON_CLK_ROCKCHIP
+ bool "Rockchip clock controller common support"
+ depends on ARCH_ROCKCHIP
+ default ARCH_ROCKCHIP
+ help
+ Say y here to enable common clock controller for Rockchip platforms.
+
+if COMMON_CLK_ROCKCHIP
+config CLK_PX30
+ bool "Rockchip Px30 clock controller support"
+ default y
+ help
+ Build the driver for Px30 Clock Driver.
+
+config CLK_RV110X
+ bool "Rockchip Rv110x clock controller support"
+ default y
+ help
+ Build the driver for Rv110x Clock Driver.
+
+config CLK_RK3036
+ bool "Rockchip Rk3036 clock controller support"
+ default y
+ help
+ Build the driver for Rk3036 Clock Driver.
+
+config CLK_RK312X
+ bool "Rockchip Rk312x clock controller support"
+ default y
+ help
+ Build the driver for Rk312x Clock Driver.
+
+config CLK_RK3188
+ bool "Rockchip Rk3188 clock controller support"
+ default y
+ help
+ Build the driver for Rk3188 Clock Driver.
+
+config CLK_RK322X
+ bool "Rockchip Rk322x clock controller support"
+ default y
+ help
+ Build the driver for Rk322x Clock Driver.
+
+config CLK_RK3288
+ bool "Rockchip Rk3288 clock controller support"
+ depends on ARM
+ default y
+ help
+ Build the driver for Rk3288 Clock Driver.
+
+config CLK_RK3308
+ bool "Rockchip Rk3308 clock controller support"
+ default y
+ help
+ Build the driver for Rk3308 Clock Driver.
+
+config CLK_RK3328
+ bool "Rockchip Rk3328 clock controller support"
+ default y
+ help
+ Build the driver for Rk3328 Clock Driver.
+
+config CLK_RK3368
+ bool "Rockchip Rk3368 clock controller support"
+ default y
+ help
+ Build the driver for Rk3368 Clock Driver.
+
+config CLK_RK3399
+ tristate "Rockchip Rk3399 clock controller support"
+ default y
+ help
+ Build the driver for Rk3399 Clock Driver.
+endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 7c5b5813a87c..a99e4d9bbae1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,24 +3,26 @@
# Rockchip Clock specific Makefile
#
-obj-y += clk.o
-obj-y += clk-pll.o
-obj-y += clk-cpu.o
-obj-y += clk-half-divider.o
-obj-y += clk-inverter.o
-obj-y += clk-mmc-phase.o
-obj-y += clk-muxgrf.o
-obj-y += clk-ddr.o
-obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
+obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
-obj-y += clk-px30.o
-obj-y += clk-rv1108.o
-obj-y += clk-rk3036.o
-obj-y += clk-rk3128.o
-obj-y += clk-rk3188.o
-obj-y += clk-rk3228.o
-obj-y += clk-rk3288.o
-obj-y += clk-rk3308.o
-obj-y += clk-rk3328.o
-obj-y += clk-rk3368.o
-obj-y += clk-rk3399.o
+clk-rockchip-y += clk.o
+clk-rockchip-y += clk-pll.o
+clk-rockchip-y += clk-cpu.o
+clk-rockchip-y += clk-half-divider.o
+clk-rockchip-y += clk-inverter.o
+clk-rockchip-y += clk-mmc-phase.o
+clk-rockchip-y += clk-muxgrf.o
+clk-rockchip-y += clk-ddr.o
+clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
+
+obj-$(CONFIG_CLK_PX30) += clk-px30.o
+obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
+obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
+obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
+obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
+obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o
+obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o
+obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
+obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
+obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
+obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 5/6] clk: rockchip: fix the clk config to support module build
2020-09-14 2:23 ` [PATCH v4 5/6] clk: rockchip: fix the clk config to support module build Elaine Zhang
@ 2020-09-15 0:42 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:42 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:23:04)
> use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
> use CONFIG_CLK_RKXX for Rk soc clk driver.
> Mark CONFIG_CLK_RK3399 to "tristate",
> to support building Rk3399 SoC clock driver as module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 6/6] clk: rockchip: rk3399: Support module build
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
` (4 preceding siblings ...)
2020-09-14 2:23 ` [PATCH v4 5/6] clk: rockchip: fix the clk config to support module build Elaine Zhang
@ 2020-09-14 2:23 ` Elaine Zhang
2020-09-15 0:42 ` Stephen Boyd
2020-09-22 13:35 ` [PATCH v4 0/6] clk: rockchip: " Heiko Stuebner
6 siblings, 1 reply; 14+ messages in thread
From: Elaine Zhang @ 2020-09-14 2:23 UTC (permalink / raw)
To: heiko
Cc: huangtao, xf, sboyd, mturquette, Elaine Zhang, linux-kernel,
linux-clk, kever.yang, linux-rockchip, xxx
support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 56 +++++++++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..7df2f1e00347 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
*/
#include <linux/clk-provider.h>
+#include <linux/module.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/rk3399-cru.h>
@@ -1600,3 +1602,57 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
rockchip_clk_of_add_provider(np, ctx);
}
CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+struct clk_rk3399_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
+ .inits = rk3399_pmu_clk_init,
+};
+
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
+ .inits = rk3399_clk_init,
+};
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+ {
+ .compatible = "rockchip,rk3399-cru",
+ .data = &clk_rk3399_cru_init,
+ }, {
+ .compatible = "rockchip,rk3399-pmucru",
+ .data = &clk_rk3399_pmucru_init,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *match;
+ const struct clk_rk3399_inits *init_data;
+
+ match = of_match_device(clk_rk3399_match_table, &pdev->dev);
+ if (!match || !match->data)
+ return -EINVAL;
+
+ init_data = match->data;
+ if (init_data->inits)
+ init_data->inits(np);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3399_driver = {
+ .driver = {
+ .name = "clk-rk3399",
+ .of_match_table = clk_rk3399_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
--
2.17.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 6/6] clk: rockchip: rk3399: Support module build
2020-09-14 2:23 ` [PATCH v4 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
@ 2020-09-15 0:42 ` Stephen Boyd
0 siblings, 0 replies; 14+ messages in thread
From: Stephen Boyd @ 2020-09-15 0:42 UTC (permalink / raw)
To: Elaine Zhang, heiko
Cc: huangtao, xf, mturquette, Elaine Zhang, linux-kernel, linux-clk,
kever.yang, linux-rockchip, xxx
Quoting Elaine Zhang (2020-09-13 19:23:16)
> support CLK_OF_DECLARE and builtin_platform_driver_probe
> double clk init method.
> add module author, description and license to support building
> Soc Rk3399 clock driver as module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 0/6] clk: rockchip: Support module build
2020-09-14 2:22 [PATCH v4 0/6] clk: rockchip: Support module build Elaine Zhang
` (5 preceding siblings ...)
2020-09-14 2:23 ` [PATCH v4 6/6] clk: rockchip: rk3399: Support " Elaine Zhang
@ 2020-09-22 13:35 ` Heiko Stuebner
6 siblings, 0 replies; 14+ messages in thread
From: Heiko Stuebner @ 2020-09-22 13:35 UTC (permalink / raw)
To: Elaine Zhang
Cc: huangtao, Heiko Stuebner, xf, sboyd, linux-kernel, xxx,
kever.yang, linux-clk, linux-rockchip, mturquette
On Mon, 14 Sep 2020 10:22:19 +0800, Elaine Zhang wrote:
> Export some APIs for module drivers.
> Fix the clock config to support module build.
> Fix the clk driver init, add module author, description
> and license to support building RK3399 SoC clock driver as module.
>
> Change in V2:
> [PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value.
> [PATCH v2 6/6]: store a function pointer in the match data.
>
> [...]
Applied, thanks!
[1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
commit: 63207c37eac4f15fdebac14685a315c259c0a780
[2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()
commit: f73907de3493b94d80af5122bcacc98f0e7b295b
[3/6] clk: rockchip: Export rockchip_register_softrst()
commit: 37353491d1a8c207685c138c3640bd43864b70d9
[4/6] clk: rockchip: Export some clock common APIs for module drivers
commit: ea650c26611dd61adfcc8647d6144f2c9f453d90
[5/6] clk: rockchip: fix the clk config to support module build
commit: 4d98ed1e126495016f2a3ef4db6379855c4aacf2
[6/6] clk: rockchip: rk3399: Support module build
commit: 70d839e2761d22eba6facdb3b65faea4d57f355d
I did some minor tweaks:
- in the Kconfig texts "Rk" -> "RK"
- made the rk3399 entry bool in patch 5
so that it stays correct when a bisection lands between
patches 5 and 6
- made in tristate in patch6 which adds the rest of module
elements
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
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^ permalink raw reply [flat|nested] 14+ messages in thread