[PATCH v2 0/6] clk: rockchip: Support module build

[PATCH v2 0/6] clk: rockchip: Support module build

[Elaine Zhang]

Export some APIs for module drivers.
Fix the clock config to support module build.
Fix the clk driver init, add module author, description
and license to support building RK3399 SoC clock driver as module.

Change in V2:
[PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value.
[PATCH v2 6/6]: store a function pointer in the match data.

Elaine Zhang (6):
  clk: rockchip: Use clk_hw_register_composite instead of
    clk_register_composite calls
  clk: rockchip: Export rockchip_clk_register_ddrclk()
  clk: rockchip: Export rockchip_register_softrst()
  clk: rockchip: Export some clock common APIs for module drivers
  clk: rockchip: fix the clk config to support module build
  clk: rockchip: rk3399: Support module build

 drivers/clk/Kconfig                     |   1 +
 drivers/clk/rockchip/Kconfig            |  78 +++++++++++++++++
 drivers/clk/rockchip/Makefile           |  42 ++++-----
 drivers/clk/rockchip/clk-ddr.c          |   1 +
 drivers/clk/rockchip/clk-half-divider.c |  18 ++--
 drivers/clk/rockchip/clk-rk3399.c       |  55 ++++++++++++
 drivers/clk/rockchip/clk.c              | 110 +++++++++++++-----------
 drivers/clk/rockchip/softrst.c          |   7 +-
 8 files changed, 229 insertions(+), 83 deletions(-)
 create mode 100644 drivers/clk/rockchip/Kconfig

-- 
2.17.1




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[PATCH v2 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

[Elaine Zhang]

clk_hw_register_composite it's already exported.
Preparation for compilation of rK common clock drivers into modules.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-half-divider.c | 18 ++++----
 drivers/clk/rockchip/clk.c              | 58 ++++++++++++-------------
 2 files changed, 38 insertions(+), 38 deletions(-)

diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b333fc28c94b..e97fd3dfbae7 100644
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
 					  unsigned long flags,
 					  spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_mux *mux = NULL;
 	struct clk_gate *gate = NULL;
 	struct clk_divider *div = NULL;
@@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
 		div_ops = &clk_half_divider_ops;
 	}
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     mux ? &mux->hw : NULL, mux_ops,
-				     div ? &div->hw : NULL, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags);
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       mux ? &mux->hw : NULL, mux_ops,
+				       div ? &div->hw : NULL, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags);
+	if (IS_ERR(hw))
+		goto err_div;
 
-	return clk;
+	return hw->clk;
 err_div:
 	kfree(gate);
 err_gate:
 	kfree(mux);
-	return ERR_PTR(-ENOMEM);
+	return ERR_CAST(hw);
 }
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 546e810c3560..b51f320e5733 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
 		u8 gate_shift, u8 gate_flags, unsigned long flags,
 		spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_mux *mux = NULL;
 	struct clk_gate *gate = NULL;
 	struct clk_divider *div = NULL;
@@ -100,25 +100,22 @@ static struct clk *rockchip_clk_register_branch(const char *name,
 						: &clk_divider_ops;
 	}
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     mux ? &mux->hw : NULL, mux_ops,
-				     div ? &div->hw : NULL, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags);
-
-	if (IS_ERR(clk)) {
-		ret = PTR_ERR(clk);
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       mux ? &mux->hw : NULL, mux_ops,
+				       div ? &div->hw : NULL, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags);
+	if (IS_ERR(hw))
 		goto err_composite;
-	}
 
-	return clk;
+	return hw->clk;
 err_composite:
 	kfree(div);
 err_div:
 	kfree(gate);
 err_gate:
 	kfree(mux);
-	return ERR_PTR(ret);
+	return ERR_CAST(hw);
 }
 
 struct rockchip_clk_frac {
@@ -214,8 +211,8 @@ static struct clk *rockchip_clk_register_frac_branch(
 		unsigned long flags, struct rockchip_clk_branch *child,
 		spinlock_t *lock)
 {
+	struct clk_hw *hw;
 	struct rockchip_clk_frac *frac;
-	struct clk *clk;
 	struct clk_gate *gate = NULL;
 	struct clk_fractional_divider *div = NULL;
 	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
@@ -255,14 +252,14 @@ static struct clk *rockchip_clk_register_frac_branch(
 	div->approximation = rockchip_fractional_approximation;
 	div_ops = &clk_fractional_divider_ops;
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     NULL, NULL,
-				     &div->hw, div_ops,
-				     gate ? &gate->hw : NULL, gate_ops,
-				     flags | CLK_SET_RATE_UNGATE);
-	if (IS_ERR(clk)) {
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       NULL, NULL,
+				       &div->hw, div_ops,
+				       gate ? &gate->hw : NULL, gate_ops,
+				       flags | CLK_SET_RATE_UNGATE);
+	if (IS_ERR(hw)) {
 		kfree(frac);
-		return clk;
+		return ERR_CAST(hw);
 	}
 
 	if (child) {
@@ -292,7 +289,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 		mux_clk = clk_register(NULL, &frac_mux->hw);
 		if (IS_ERR(mux_clk)) {
 			kfree(frac);
-			return clk;
+			return mux_clk;
 		}
 
 		rockchip_clk_add_lookup(ctx, mux_clk, child->id);
@@ -301,7 +298,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 		if (frac->mux_frac_idx >= 0) {
 			pr_debug("%s: found fractional parent in mux at pos %d\n",
 				 __func__, frac->mux_frac_idx);
-			ret = clk_notifier_register(clk, &frac->clk_nb);
+			ret = clk_notifier_register(hw->clk, &frac->clk_nb);
 			if (ret)
 				pr_err("%s: failed to register clock notifier for %s\n",
 						__func__, name);
@@ -311,7 +308,7 @@ static struct clk *rockchip_clk_register_frac_branch(
 		}
 	}
 
-	return clk;
+	return hw->clk;
 }
 
 static struct clk *rockchip_clk_register_factor_branch(const char *name,
@@ -320,7 +317,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
 		int gate_offset, u8 gate_shift, u8 gate_flags,
 		unsigned long flags, spinlock_t *lock)
 {
-	struct clk *clk;
+	struct clk_hw *hw;
 	struct clk_gate *gate = NULL;
 	struct clk_fixed_factor *fix = NULL;
 
@@ -349,16 +346,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
 	fix->mult = mult;
 	fix->div = div;
 
-	clk = clk_register_composite(NULL, name, parent_names, num_parents,
-				     NULL, NULL,
-				     &fix->hw, &clk_fixed_factor_ops,
-				     &gate->hw, &clk_gate_ops, flags);
-	if (IS_ERR(clk)) {
+	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+				       NULL, NULL,
+				       &fix->hw, &clk_fixed_factor_ops,
+				       &gate->hw, &clk_gate_ops, flags);
+	if (IS_ERR(hw)) {
 		kfree(fix);
 		kfree(gate);
+		return ERR_CAST(hw);
 	}
 
-	return clk;
+	return hw->clk;
 }
 
 struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
-- 
2.17.1




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Re: [PATCH v2 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

[Kever Yang]

Hi Elaine,

On 2020/9/3 下午2:31, Elaine Zhang wrote:
> clk_hw_register_composite it's already exported.
> Preparation for compilation of rK common clock drivers into modules.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-half-divider.c | 18 ++++----
>   drivers/clk/rockchip/clk.c              | 58 ++++++++++++-------------
>   2 files changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
> index b333fc28c94b..e97fd3dfbae7 100644
> --- a/drivers/clk/rockchip/clk-half-divider.c
> +++ b/drivers/clk/rockchip/clk-half-divider.c
> @@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
>   					  unsigned long flags,
>   					  spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_mux *mux = NULL;
>   	struct clk_gate *gate = NULL;
>   	struct clk_divider *div = NULL;
> @@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
>   		div_ops = &clk_half_divider_ops;
>   	}
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     mux ? &mux->hw : NULL, mux_ops,
> -				     div ? &div->hw : NULL, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags);
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       mux ? &mux->hw : NULL, mux_ops,
> +				       div ? &div->hw : NULL, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags);
> +	if (IS_ERR(hw))
> +		goto err_div;
>   
> -	return clk;
> +	return hw->clk;
>   err_div:
>   	kfree(gate);
>   err_gate:
>   	kfree(mux);
> -	return ERR_PTR(-ENOMEM);
> +	return ERR_CAST(hw);
>   }
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index 546e810c3560..b51f320e5733 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
>   		u8 gate_shift, u8 gate_flags, unsigned long flags,
>   		spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_mux *mux = NULL;
>   	struct clk_gate *gate = NULL;
>   	struct clk_divider *div = NULL;
> @@ -100,25 +100,22 @@ static struct clk *rockchip_clk_register_branch(const char *name,
>   						: &clk_divider_ops;
>   	}
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     mux ? &mux->hw : NULL, mux_ops,
> -				     div ? &div->hw : NULL, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags);
> -
> -	if (IS_ERR(clk)) {
> -		ret = PTR_ERR(clk);
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       mux ? &mux->hw : NULL, mux_ops,
> +				       div ? &div->hw : NULL, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags);
> +	if (IS_ERR(hw))
>   		goto err_composite;
> -	}
>   
> -	return clk;
> +	return hw->clk;
>   err_composite:
>   	kfree(div);
>   err_div:
>   	kfree(gate);
>   err_gate:
>   	kfree(mux);
> -	return ERR_PTR(ret);
> +	return ERR_CAST(hw);
>   }
>   
>   struct rockchip_clk_frac {
> @@ -214,8 +211,8 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		unsigned long flags, struct rockchip_clk_branch *child,
>   		spinlock_t *lock)
>   {
> +	struct clk_hw *hw;
>   	struct rockchip_clk_frac *frac;
> -	struct clk *clk;
>   	struct clk_gate *gate = NULL;
>   	struct clk_fractional_divider *div = NULL;
>   	const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
> @@ -255,14 +252,14 @@ static struct clk *rockchip_clk_register_frac_branch(
>   	div->approximation = rockchip_fractional_approximation;
>   	div_ops = &clk_fractional_divider_ops;
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     NULL, NULL,
> -				     &div->hw, div_ops,
> -				     gate ? &gate->hw : NULL, gate_ops,
> -				     flags | CLK_SET_RATE_UNGATE);
> -	if (IS_ERR(clk)) {
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       NULL, NULL,
> +				       &div->hw, div_ops,
> +				       gate ? &gate->hw : NULL, gate_ops,
> +				       flags | CLK_SET_RATE_UNGATE);
> +	if (IS_ERR(hw)) {
>   		kfree(frac);
> -		return clk;
> +		return ERR_CAST(hw);
>   	}
>   
>   	if (child) {
> @@ -292,7 +289,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		mux_clk = clk_register(NULL, &frac_mux->hw);
>   		if (IS_ERR(mux_clk)) {
>   			kfree(frac);
> -			return clk;
> +			return mux_clk;
>   		}
>   
>   		rockchip_clk_add_lookup(ctx, mux_clk, child->id);
> @@ -301,7 +298,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		if (frac->mux_frac_idx >= 0) {
>   			pr_debug("%s: found fractional parent in mux at pos %d\n",
>   				 __func__, frac->mux_frac_idx);
> -			ret = clk_notifier_register(clk, &frac->clk_nb);
> +			ret = clk_notifier_register(hw->clk, &frac->clk_nb);
>   			if (ret)
>   				pr_err("%s: failed to register clock notifier for %s\n",
>   						__func__, name);
> @@ -311,7 +308,7 @@ static struct clk *rockchip_clk_register_frac_branch(
>   		}
>   	}
>   
> -	return clk;
> +	return hw->clk;
>   }
>   
>   static struct clk *rockchip_clk_register_factor_branch(const char *name,
> @@ -320,7 +317,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
>   		int gate_offset, u8 gate_shift, u8 gate_flags,
>   		unsigned long flags, spinlock_t *lock)
>   {
> -	struct clk *clk;
> +	struct clk_hw *hw;
>   	struct clk_gate *gate = NULL;
>   	struct clk_fixed_factor *fix = NULL;
>   
> @@ -349,16 +346,17 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
>   	fix->mult = mult;
>   	fix->div = div;
>   
> -	clk = clk_register_composite(NULL, name, parent_names, num_parents,
> -				     NULL, NULL,
> -				     &fix->hw, &clk_fixed_factor_ops,
> -				     &gate->hw, &clk_gate_ops, flags);
> -	if (IS_ERR(clk)) {
> +	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
> +				       NULL, NULL,
> +				       &fix->hw, &clk_fixed_factor_ops,
> +				       &gate->hw, &clk_gate_ops, flags);
> +	if (IS_ERR(hw)) {
>   		kfree(fix);
>   		kfree(gate);
> +		return ERR_CAST(hw);
>   	}
>   
> -	return clk;
> +	return hw->clk;
>   }
>   
>   struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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Re: [PATCH v2 1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 8485 bytes --]

Hi Elaine,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on rockchip/for-next]
[also build test WARNING on clk/clk-next v5.9-rc3 next-20200903]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Elaine-Zhang/clk-rockchip-Support-module-build/20200903-143443
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-randconfig-r014-20200902 (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/clk/rockchip/clk.c: In function 'rockchip_clk_register_branch':
>> drivers/clk/rockchip/clk.c:52:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
      52 |  int ret;
         |      ^~~

# https://github.com/0day-ci/linux/commit/47a0fbff201df1b9022204113caca1ed6da700b1
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Elaine-Zhang/clk-rockchip-Support-module-build/20200903-143443
git checkout 47a0fbff201df1b9022204113caca1ed6da700b1
vim +/ret +52 drivers/clk/rockchip/clk.c

a245fecbb80646 Heiko Stübner  2014-07-03   26  
a245fecbb80646 Heiko Stübner  2014-07-03   27  /**
a245fecbb80646 Heiko Stübner  2014-07-03   28   * Register a clock branch.
a245fecbb80646 Heiko Stübner  2014-07-03   29   * Most clock branches have a form like
a245fecbb80646 Heiko Stübner  2014-07-03   30   *
a245fecbb80646 Heiko Stübner  2014-07-03   31   * src1 --|--\
a245fecbb80646 Heiko Stübner  2014-07-03   32   *        |M |--[GATE]-[DIV]-
a245fecbb80646 Heiko Stübner  2014-07-03   33   * src2 --|--/
a245fecbb80646 Heiko Stübner  2014-07-03   34   *
a245fecbb80646 Heiko Stübner  2014-07-03   35   * sometimes without one of those components.
a245fecbb80646 Heiko Stübner  2014-07-03   36   */
1a4b1819950a27 Heiko Stübner  2014-08-27   37  static struct clk *rockchip_clk_register_branch(const char *name,
03ae1747869437 Heiko Stuebner 2016-04-19   38  		const char *const *parent_names, u8 num_parents,
03ae1747869437 Heiko Stuebner 2016-04-19   39  		void __iomem *base,
a245fecbb80646 Heiko Stübner  2014-07-03   40  		int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
1f55660ff80522 Finley Xiao    2019-04-03   41  		int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
a245fecbb80646 Heiko Stübner  2014-07-03   42  		struct clk_div_table *div_table, int gate_offset,
a245fecbb80646 Heiko Stübner  2014-07-03   43  		u8 gate_shift, u8 gate_flags, unsigned long flags,
a245fecbb80646 Heiko Stübner  2014-07-03   44  		spinlock_t *lock)
a245fecbb80646 Heiko Stübner  2014-07-03   45  {
47a0fbff201df1 Elaine Zhang   2020-09-03   46  	struct clk_hw *hw;
a245fecbb80646 Heiko Stübner  2014-07-03   47  	struct clk_mux *mux = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   48  	struct clk_gate *gate = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   49  	struct clk_divider *div = NULL;
a245fecbb80646 Heiko Stübner  2014-07-03   50  	const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
a245fecbb80646 Heiko Stübner  2014-07-03   51  			     *gate_ops = NULL;
fd3cbbfb76a422 Shawn Lin      2018-02-28  @52  	int ret;
a245fecbb80646 Heiko Stübner  2014-07-03   53  
a245fecbb80646 Heiko Stübner  2014-07-03   54  	if (num_parents > 1) {
a245fecbb80646 Heiko Stübner  2014-07-03   55  		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
a245fecbb80646 Heiko Stübner  2014-07-03   56  		if (!mux)
a245fecbb80646 Heiko Stübner  2014-07-03   57  			return ERR_PTR(-ENOMEM);
a245fecbb80646 Heiko Stübner  2014-07-03   58  
a245fecbb80646 Heiko Stübner  2014-07-03   59  		mux->reg = base + muxdiv_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   60  		mux->shift = mux_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   61  		mux->mask = BIT(mux_width) - 1;
a245fecbb80646 Heiko Stübner  2014-07-03   62  		mux->flags = mux_flags;
a245fecbb80646 Heiko Stübner  2014-07-03   63  		mux->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   64  		mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
a245fecbb80646 Heiko Stübner  2014-07-03   65  							: &clk_mux_ops;
a245fecbb80646 Heiko Stübner  2014-07-03   66  	}
a245fecbb80646 Heiko Stübner  2014-07-03   67  
a245fecbb80646 Heiko Stübner  2014-07-03   68  	if (gate_offset >= 0) {
a245fecbb80646 Heiko Stübner  2014-07-03   69  		gate = kzalloc(sizeof(*gate), GFP_KERNEL);
fd3cbbfb76a422 Shawn Lin      2018-02-28   70  		if (!gate) {
fd3cbbfb76a422 Shawn Lin      2018-02-28   71  			ret = -ENOMEM;
2467b6745e0ae9 Shawn Lin      2016-02-02   72  			goto err_gate;
fd3cbbfb76a422 Shawn Lin      2018-02-28   73  		}
a245fecbb80646 Heiko Stübner  2014-07-03   74  
a245fecbb80646 Heiko Stübner  2014-07-03   75  		gate->flags = gate_flags;
a245fecbb80646 Heiko Stübner  2014-07-03   76  		gate->reg = base + gate_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   77  		gate->bit_idx = gate_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   78  		gate->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   79  		gate_ops = &clk_gate_ops;
a245fecbb80646 Heiko Stübner  2014-07-03   80  	}
a245fecbb80646 Heiko Stübner  2014-07-03   81  
a245fecbb80646 Heiko Stübner  2014-07-03   82  	if (div_width > 0) {
a245fecbb80646 Heiko Stübner  2014-07-03   83  		div = kzalloc(sizeof(*div), GFP_KERNEL);
fd3cbbfb76a422 Shawn Lin      2018-02-28   84  		if (!div) {
fd3cbbfb76a422 Shawn Lin      2018-02-28   85  			ret = -ENOMEM;
2467b6745e0ae9 Shawn Lin      2016-02-02   86  			goto err_div;
fd3cbbfb76a422 Shawn Lin      2018-02-28   87  		}
a245fecbb80646 Heiko Stübner  2014-07-03   88  
a245fecbb80646 Heiko Stübner  2014-07-03   89  		div->flags = div_flags;
1f55660ff80522 Finley Xiao    2019-04-03   90  		if (div_offset)
1f55660ff80522 Finley Xiao    2019-04-03   91  			div->reg = base + div_offset;
1f55660ff80522 Finley Xiao    2019-04-03   92  		else
a245fecbb80646 Heiko Stübner  2014-07-03   93  			div->reg = base + muxdiv_offset;
a245fecbb80646 Heiko Stübner  2014-07-03   94  		div->shift = div_shift;
a245fecbb80646 Heiko Stübner  2014-07-03   95  		div->width = div_width;
a245fecbb80646 Heiko Stübner  2014-07-03   96  		div->lock = lock;
a245fecbb80646 Heiko Stübner  2014-07-03   97  		div->table = div_table;
50359819794b4a Heiko Stuebner 2016-01-21   98  		div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
50359819794b4a Heiko Stuebner 2016-01-21   99  						? &clk_divider_ro_ops
50359819794b4a Heiko Stuebner 2016-01-21  100  						: &clk_divider_ops;
a245fecbb80646 Heiko Stübner  2014-07-03  101  	}
a245fecbb80646 Heiko Stübner  2014-07-03  102  
47a0fbff201df1 Elaine Zhang   2020-09-03  103  	hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
a245fecbb80646 Heiko Stübner  2014-07-03  104  				       mux ? &mux->hw : NULL, mux_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  105  				       div ? &div->hw : NULL, div_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  106  				       gate ? &gate->hw : NULL, gate_ops,
a245fecbb80646 Heiko Stübner  2014-07-03  107  				       flags);
47a0fbff201df1 Elaine Zhang   2020-09-03  108  	if (IS_ERR(hw))
fd3cbbfb76a422 Shawn Lin      2018-02-28  109  		goto err_composite;
fd3cbbfb76a422 Shawn Lin      2018-02-28  110  
47a0fbff201df1 Elaine Zhang   2020-09-03  111  	return hw->clk;
fd3cbbfb76a422 Shawn Lin      2018-02-28  112  err_composite:
fd3cbbfb76a422 Shawn Lin      2018-02-28  113  	kfree(div);
2467b6745e0ae9 Shawn Lin      2016-02-02  114  err_div:
2467b6745e0ae9 Shawn Lin      2016-02-02  115  	kfree(gate);
2467b6745e0ae9 Shawn Lin      2016-02-02  116  err_gate:
2467b6745e0ae9 Shawn Lin      2016-02-02  117  	kfree(mux);
47a0fbff201df1 Elaine Zhang   2020-09-03  118  	return ERR_CAST(hw);
a245fecbb80646 Heiko Stübner  2014-07-03  119  }
a245fecbb80646 Heiko Stübner  2014-07-03  120  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 32398 bytes --]

[-- Attachment #3: Type: text/plain, Size: 170 bytes --]

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[PATCH v2 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()

[Elaine Zhang]

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-ddr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index 9273bce4d7b6..282b6f22eb22 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
 
 	return clk;
 }
+EXPORT_SYMBOL(rockchip_clk_register_ddrclk);
-- 
2.17.1




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Re: [PATCH v2 2/6] clk: rockchip: Export rockchip_clk_register_ddrclk()

[Kever Yang]

On 2020/9/3 下午2:31, Elaine Zhang wrote:
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module..
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-ddr.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
> index 9273bce4d7b6..282b6f22eb22 100644
> --- a/drivers/clk/rockchip/clk-ddr.c
> +++ b/drivers/clk/rockchip/clk-ddr.c
> @@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
>   
>   	return clk;
>   }
> +EXPORT_SYMBOL(rockchip_clk_register_ddrclk);

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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[PATCH v2 3/6] clk: rockchip: Export rockchip_register_softrst()

[Elaine Zhang]

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module..

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/softrst.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
index 5f1ff5e47c4f..caba9055090b 100644
--- a/drivers/clk/rockchip/softrst.c
+++ b/drivers/clk/rockchip/softrst.c
@@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
 	.deassert	= rockchip_softrst_deassert,
 };
 
-void __init rockchip_register_softrst(struct device_node *np,
-				      unsigned int num_regs,
-				      void __iomem *base, u8 flags)
+void rockchip_register_softrst(struct device_node *np,
+			       unsigned int num_regs,
+			       void __iomem *base, u8 flags)
 {
 	struct rockchip_softrst *softrst;
 	int ret;
@@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
 		kfree(softrst);
 	}
 };
+EXPORT_SYMBOL(rockchip_register_softrst);
-- 
2.17.1




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Re: [PATCH v2 3/6] clk: rockchip: Export rockchip_register_softrst()

[Kever Yang]

On 2020/9/3 下午2:31, Elaine Zhang wrote:
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module..
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/softrst.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
> index 5f1ff5e47c4f..caba9055090b 100644
> --- a/drivers/clk/rockchip/softrst.c
> +++ b/drivers/clk/rockchip/softrst.c
> @@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
>   	.deassert	= rockchip_softrst_deassert,
>   };
>   
> -void __init rockchip_register_softrst(struct device_node *np,
> -				      unsigned int num_regs,
> -				      void __iomem *base, u8 flags)
> +void rockchip_register_softrst(struct device_node *np,
> +			       unsigned int num_regs,
> +			       void __iomem *base, u8 flags)
>   {
>   	struct rockchip_softrst *softrst;
>   	int ret;
> @@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
>   		kfree(softrst);
>   	}
>   };
> +EXPORT_SYMBOL(rockchip_register_softrst);

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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[PATCH v2 4/6] clk: rockchip: Export some clock common APIs for module drivers

[Elaine Zhang]

This is used by the Rockchip clk driver, export it to allow that
driver to be compiled as a module.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++----------------
 1 file changed, 30 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index b51f320e5733..b7664224e64a 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -359,8 +359,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
 	return hw->clk;
 }
 
-struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
-			void __iomem *base, unsigned long nr_clks)
+struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+						void __iomem *base,
+						unsigned long nr_clks)
 {
 	struct rockchip_clk_provider *ctx;
 	struct clk **clk_table;
@@ -392,14 +393,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
 	kfree(ctx);
 	return ERR_PTR(-ENOMEM);
 }
+EXPORT_SYMBOL(rockchip_clk_init);
 
-void __init rockchip_clk_of_add_provider(struct device_node *np,
-				struct rockchip_clk_provider *ctx)
+void rockchip_clk_of_add_provider(struct device_node *np,
+				  struct rockchip_clk_provider *ctx)
 {
 	if (of_clk_add_provider(np, of_clk_src_onecell_get,
 				&ctx->clk_data))
 		pr_err("%s: could not register clk provider\n", __func__);
 }
+EXPORT_SYMBOL(rockchip_clk_of_add_provider);
 
 void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 			     struct clk *clk, unsigned int id)
@@ -407,8 +410,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
 	if (ctx->clk_data.clks && id)
 		ctx->clk_data.clks[id] = clk;
 }
+EXPORT_SYMBOL(rockchip_clk_add_lookup);
 
-void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 				struct rockchip_pll_clock *list,
 				unsigned int nr_pll, int grf_lock_offset)
 {
@@ -431,11 +435,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
 		rockchip_clk_add_lookup(ctx, clk, list->id);
 	}
 }
+EXPORT_SYMBOL(rockchip_clk_register_plls);
 
-void __init rockchip_clk_register_branches(
-				      struct rockchip_clk_provider *ctx,
-				      struct rockchip_clk_branch *list,
-				      unsigned int nr_clk)
+void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+				    struct rockchip_clk_branch *list,
+				    unsigned int nr_clk)
 {
 	struct clk *clk = NULL;
 	unsigned int idx;
@@ -564,14 +568,15 @@ void __init rockchip_clk_register_branches(
 		rockchip_clk_add_lookup(ctx, clk, list->id);
 	}
 }
-
-void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
-			unsigned int lookup_id,
-			const char *name, const char *const *parent_names,
-			u8 num_parents,
-			const struct rockchip_cpuclk_reg_data *reg_data,
-			const struct rockchip_cpuclk_rate_table *rates,
-			int nrates)
+EXPORT_SYMBOL(rockchip_clk_register_branches);
+
+void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+				  unsigned int lookup_id,
+				  const char *name, const char *const *parent_names,
+				  u8 num_parents,
+				  const struct rockchip_cpuclk_reg_data *reg_data,
+				  const struct rockchip_cpuclk_rate_table *rates,
+				  int nrates)
 {
 	struct clk *clk;
 
@@ -586,9 +591,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
 
 	rockchip_clk_add_lookup(ctx, clk, lookup_id);
 }
+EXPORT_SYMBOL(rockchip_clk_register_armclk);
 
-void __init rockchip_clk_protect_critical(const char *const clocks[],
-					  int nclocks)
+void rockchip_clk_protect_critical(const char *const clocks[],
+				   int nclocks)
 {
 	int i;
 
@@ -600,6 +606,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
 			clk_prepare_enable(clk);
 	}
 }
+EXPORT_SYMBOL(rockchip_clk_protect_critical);
 
 static void __iomem *rst_base;
 static unsigned int reg_restart;
@@ -619,10 +626,10 @@ static struct notifier_block rockchip_restart_handler = {
 	.priority = 128,
 };
 
-void __init
+void
 rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
-					       unsigned int reg,
-					       void (*cb)(void))
+				   unsigned int reg,
+				   void (*cb)(void))
 {
 	int ret;
 
@@ -634,3 +641,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
 		pr_err("%s: cannot register restart handler, %d\n",
 		       __func__, ret);
 }
+EXPORT_SYMBOL(rockchip_register_restart_notifier);
-- 
2.17.1




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Re: [PATCH v2 4/6] clk: rockchip: Export some clock common APIs for module drivers

[Kever Yang]

On 2020/9/3 下午2:31, Elaine Zhang wrote:
> This is used by the Rockchip clk driver, export it to allow that
> driver to be compiled as a module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk.c | 52 ++++++++++++++++++++++----------------
>   1 file changed, 30 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
> index b51f320e5733..b7664224e64a 100644
> --- a/drivers/clk/rockchip/clk.c
> +++ b/drivers/clk/rockchip/clk.c
> @@ -359,8 +359,9 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
>   	return hw->clk;
>   }
>   
> -struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
> -			void __iomem *base, unsigned long nr_clks)
> +struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
> +						void __iomem *base,
> +						unsigned long nr_clks)
>   {
>   	struct rockchip_clk_provider *ctx;
>   	struct clk **clk_table;
> @@ -392,14 +393,16 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
>   	kfree(ctx);
>   	return ERR_PTR(-ENOMEM);
>   }
> +EXPORT_SYMBOL(rockchip_clk_init);
>   
> -void __init rockchip_clk_of_add_provider(struct device_node *np,
> -				struct rockchip_clk_provider *ctx)
> +void rockchip_clk_of_add_provider(struct device_node *np,
> +				  struct rockchip_clk_provider *ctx)
>   {
>   	if (of_clk_add_provider(np, of_clk_src_onecell_get,
>   				&ctx->clk_data))
>   		pr_err("%s: could not register clk provider\n", __func__);
>   }
> +EXPORT_SYMBOL(rockchip_clk_of_add_provider);
>   
>   void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
>   			     struct clk *clk, unsigned int id)
> @@ -407,8 +410,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
>   	if (ctx->clk_data.clks && id)
>   		ctx->clk_data.clks[id] = clk;
>   }
> +EXPORT_SYMBOL(rockchip_clk_add_lookup);
>   
> -void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
> +void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
>   				struct rockchip_pll_clock *list,
>   				unsigned int nr_pll, int grf_lock_offset)
>   {
> @@ -431,11 +435,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
>   		rockchip_clk_add_lookup(ctx, clk, list->id);
>   	}
>   }
> +EXPORT_SYMBOL(rockchip_clk_register_plls);
>   
> -void __init rockchip_clk_register_branches(
> -				      struct rockchip_clk_provider *ctx,
> -				      struct rockchip_clk_branch *list,
> -				      unsigned int nr_clk)
> +void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
> +				    struct rockchip_clk_branch *list,
> +				    unsigned int nr_clk)
>   {
>   	struct clk *clk = NULL;
>   	unsigned int idx;
> @@ -564,14 +568,15 @@ void __init rockchip_clk_register_branches(
>   		rockchip_clk_add_lookup(ctx, clk, list->id);
>   	}
>   }
> -
> -void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
> -			unsigned int lookup_id,
> -			const char *name, const char *const *parent_names,
> -			u8 num_parents,
> -			const struct rockchip_cpuclk_reg_data *reg_data,
> -			const struct rockchip_cpuclk_rate_table *rates,
> -			int nrates)
> +EXPORT_SYMBOL(rockchip_clk_register_branches);
> +
> +void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
> +				  unsigned int lookup_id,
> +				  const char *name, const char *const *parent_names,
> +				  u8 num_parents,
> +				  const struct rockchip_cpuclk_reg_data *reg_data,
> +				  const struct rockchip_cpuclk_rate_table *rates,
> +				  int nrates)
>   {
>   	struct clk *clk;
>   
> @@ -586,9 +591,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
>   
>   	rockchip_clk_add_lookup(ctx, clk, lookup_id);
>   }
> +EXPORT_SYMBOL(rockchip_clk_register_armclk);
>   
> -void __init rockchip_clk_protect_critical(const char *const clocks[],
> -					  int nclocks)
> +void rockchip_clk_protect_critical(const char *const clocks[],
> +				   int nclocks)
>   {
>   	int i;
>   
> @@ -600,6 +606,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
>   			clk_prepare_enable(clk);
>   	}
>   }
> +EXPORT_SYMBOL(rockchip_clk_protect_critical);
>   
>   static void __iomem *rst_base;
>   static unsigned int reg_restart;
> @@ -619,10 +626,10 @@ static struct notifier_block rockchip_restart_handler = {
>   	.priority = 128,
>   };
>   
> -void __init
> +void
>   rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
> -					       unsigned int reg,
> -					       void (*cb)(void))
> +				   unsigned int reg,
> +				   void (*cb)(void))
>   {
>   	int ret;
>   
> @@ -634,3 +641,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
>   		pr_err("%s: cannot register restart handler, %d\n",
>   		       __func__, ret);
>   }
> +EXPORT_SYMBOL(rockchip_register_restart_notifier);


This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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[PATCH v2 5/6] clk: rockchip: fix the clk config to support module build

[Elaine Zhang]

use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
use CONFIG_CLK_RKXX for Rk soc clk driver.
Mark configuration to "tristate",
to support building Rk SoCs clock driver as module.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/Kconfig           |  1 +
 drivers/clk/rockchip/Kconfig  | 78 +++++++++++++++++++++++++++++++++++
 drivers/clk/rockchip/Makefile | 42 ++++++++++---------
 3 files changed, 101 insertions(+), 20 deletions(-)
 create mode 100644 drivers/clk/rockchip/Kconfig

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4026fac9fac3..b41aaed9bd51 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/qcom/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/rockchip/Kconfig"
 source "drivers/clk/samsung/Kconfig"
 source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/sprd/Kconfig"
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
new file mode 100644
index 000000000000..53a44396bc35
--- /dev/null
+++ b/drivers/clk/rockchip/Kconfig
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+# common clock support for ROCKCHIP SoC family.
+
+config COMMON_CLK_ROCKCHIP
+	tristate "Rockchip clock controller common support"
+	depends on ARCH_ROCKCHIP
+	default ARCH_ROCKCHIP
+	help
+	  Say y here to enable common clock controller.
+
+if COMMON_CLK_ROCKCHIP
+config CLK_PX30
+	tristate "Rockchip Px30 clock controller support"
+	default y
+	help
+	  Build the driver for Px30 Clock Driver.
+
+config CLK_RV110X
+	tristate "Rockchip Rv110x clock controller support"
+	default y
+	help
+	  Build the driver for Rv110x Clock Driver.
+
+config CLK_RK3036
+	tristate "Rockchip Rk3036 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3036 Clock Driver.
+
+config CLK_RK312X
+	tristate "Rockchip Rk312x clock controller support"
+	default y
+	help
+	  Build the driver for Rk312x Clock Driver.
+
+config CLK_RK3188
+	tristate "Rockchip Rk3188 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3188 Clock Driver.
+
+config CLK_RK322X
+	tristate "Rockchip Rk322x clock controller support"
+	default y
+	help
+	  Build the driver for Rk322x Clock Driver.
+
+config CLK_RK3288
+	tristate "Rockchip Rk3288 clock controller support"
+	depends on ARM
+	default y
+	help
+	  Build the driver for Rk3288 Clock Driver.
+
+config CLK_RK3308
+	tristate "Rockchip Rk3308 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3308 Clock Driver.
+
+config CLK_RK3328
+	tristate "Rockchip Rk3328 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3328 Clock Driver.
+
+config CLK_RK3368
+	tristate "Rockchip Rk3368 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3368 Clock Driver.
+
+config CLK_RK3399
+	tristate "Rockchip Rk3399 clock controller support"
+	default y
+	help
+	  Build the driver for Rk3399 Clock Driver.
+endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 7c5b5813a87c..a99e4d9bbae1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,24 +3,26 @@
 # Rockchip Clock specific Makefile
 #
 
-obj-y	+= clk.o
-obj-y	+= clk-pll.o
-obj-y	+= clk-cpu.o
-obj-y	+= clk-half-divider.o
-obj-y	+= clk-inverter.o
-obj-y	+= clk-mmc-phase.o
-obj-y	+= clk-muxgrf.o
-obj-y	+= clk-ddr.o
-obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o
+obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
 
-obj-y	+= clk-px30.o
-obj-y	+= clk-rv1108.o
-obj-y	+= clk-rk3036.o
-obj-y	+= clk-rk3128.o
-obj-y	+= clk-rk3188.o
-obj-y	+= clk-rk3228.o
-obj-y	+= clk-rk3288.o
-obj-y	+= clk-rk3308.o
-obj-y	+= clk-rk3328.o
-obj-y	+= clk-rk3368.o
-obj-y	+= clk-rk3399.o
+clk-rockchip-y += clk.o
+clk-rockchip-y += clk-pll.o
+clk-rockchip-y += clk-cpu.o
+clk-rockchip-y += clk-half-divider.o
+clk-rockchip-y += clk-inverter.o
+clk-rockchip-y += clk-mmc-phase.o
+clk-rockchip-y += clk-muxgrf.o
+clk-rockchip-y += clk-ddr.o
+clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
+
+obj-$(CONFIG_CLK_PX30)          += clk-px30.o
+obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
+obj-$(CONFIG_CLK_RK3036)        += clk-rk3036.o
+obj-$(CONFIG_CLK_RK312X)        += clk-rk3128.o
+obj-$(CONFIG_CLK_RK3188)        += clk-rk3188.o
+obj-$(CONFIG_CLK_RK322X)        += clk-rk3228.o
+obj-$(CONFIG_CLK_RK3288)        += clk-rk3288.o
+obj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o
+obj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o
+obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
+obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
-- 
2.17.1




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Re: [PATCH v2 5/6] clk: rockchip: fix the clk config to support module build

[Kever Yang]

On 2020/9/3 下午2:32, Elaine Zhang wrote:
> use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers.
> use CONFIG_CLK_RKXX for Rk soc clk driver.
> Mark configuration to "tristate",
> to support building Rk SoCs clock driver as module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/Kconfig           |  1 +
>   drivers/clk/rockchip/Kconfig  | 78 +++++++++++++++++++++++++++++++++++
>   drivers/clk/rockchip/Makefile | 42 ++++++++++---------
>   3 files changed, 101 insertions(+), 20 deletions(-)
>   create mode 100644 drivers/clk/rockchip/Kconfig
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 4026fac9fac3..b41aaed9bd51 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
>   source "drivers/clk/mvebu/Kconfig"
>   source "drivers/clk/qcom/Kconfig"
>   source "drivers/clk/renesas/Kconfig"
> +source "drivers/clk/rockchip/Kconfig"
>   source "drivers/clk/samsung/Kconfig"
>   source "drivers/clk/sifive/Kconfig"
>   source "drivers/clk/sprd/Kconfig"
> diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
> new file mode 100644
> index 000000000000..53a44396bc35
> --- /dev/null
> +++ b/drivers/clk/rockchip/Kconfig
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# common clock support for ROCKCHIP SoC family.
> +
> +config COMMON_CLK_ROCKCHIP
> +	tristate "Rockchip clock controller common support"
> +	depends on ARCH_ROCKCHIP
> +	default ARCH_ROCKCHIP
> +	help
> +	  Say y here to enable common clock controller.
> +
> +if COMMON_CLK_ROCKCHIP
> +config CLK_PX30
> +	tristate "Rockchip Px30 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Px30 Clock Driver.
> +
> +config CLK_RV110X
> +	tristate "Rockchip Rv110x clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rv110x Clock Driver.
> +
> +config CLK_RK3036
> +	tristate "Rockchip Rk3036 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3036 Clock Driver.
> +
> +config CLK_RK312X
> +	tristate "Rockchip Rk312x clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk312x Clock Driver.
> +
> +config CLK_RK3188
> +	tristate "Rockchip Rk3188 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3188 Clock Driver.
> +
> +config CLK_RK322X
> +	tristate "Rockchip Rk322x clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk322x Clock Driver.
> +
> +config CLK_RK3288
> +	tristate "Rockchip Rk3288 clock controller support"
> +	depends on ARM
> +	default y
> +	help
> +	  Build the driver for Rk3288 Clock Driver.
> +
> +config CLK_RK3308
> +	tristate "Rockchip Rk3308 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3308 Clock Driver.
> +
> +config CLK_RK3328
> +	tristate "Rockchip Rk3328 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3328 Clock Driver.
> +
> +config CLK_RK3368
> +	tristate "Rockchip Rk3368 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3368 Clock Driver.
> +
> +config CLK_RK3399
> +	tristate "Rockchip Rk3399 clock controller support"
> +	default y
> +	help
> +	  Build the driver for Rk3399 Clock Driver.
> +endif
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 7c5b5813a87c..a99e4d9bbae1 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -3,24 +3,26 @@
>   # Rockchip Clock specific Makefile
>   #
>   
> -obj-y	+= clk.o
> -obj-y	+= clk-pll.o
> -obj-y	+= clk-cpu.o
> -obj-y	+= clk-half-divider.o
> -obj-y	+= clk-inverter.o
> -obj-y	+= clk-mmc-phase.o
> -obj-y	+= clk-muxgrf.o
> -obj-y	+= clk-ddr.o
> -obj-$(CONFIG_RESET_CONTROLLER)	+= softrst.o
> +obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
>   
> -obj-y	+= clk-px30.o
> -obj-y	+= clk-rv1108.o
> -obj-y	+= clk-rk3036.o
> -obj-y	+= clk-rk3128.o
> -obj-y	+= clk-rk3188.o
> -obj-y	+= clk-rk3228.o
> -obj-y	+= clk-rk3288.o
> -obj-y	+= clk-rk3308.o
> -obj-y	+= clk-rk3328.o
> -obj-y	+= clk-rk3368.o
> -obj-y	+= clk-rk3399.o
> +clk-rockchip-y += clk.o
> +clk-rockchip-y += clk-pll.o
> +clk-rockchip-y += clk-cpu.o
> +clk-rockchip-y += clk-half-divider.o
> +clk-rockchip-y += clk-inverter.o
> +clk-rockchip-y += clk-mmc-phase.o
> +clk-rockchip-y += clk-muxgrf.o
> +clk-rockchip-y += clk-ddr.o
> +clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
> +
> +obj-$(CONFIG_CLK_PX30)          += clk-px30.o
> +obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
> +obj-$(CONFIG_CLK_RK3036)        += clk-rk3036.o
> +obj-$(CONFIG_CLK_RK312X)        += clk-rk3128.o
> +obj-$(CONFIG_CLK_RK3188)        += clk-rk3188.o
> +obj-$(CONFIG_CLK_RK322X)        += clk-rk3228.o
> +obj-$(CONFIG_CLK_RK3288)        += clk-rk3288.o
> +obj-$(CONFIG_CLK_RK3308)        += clk-rk3308.o
> +obj-$(CONFIG_CLK_RK3328)        += clk-rk3328.o
> +obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
> +obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 6/6] clk: rockchip: rk3399: Support module build

[Elaine Zhang]

support CLK_OF_DECLARE and builtin_platform_driver_probe
double clk init method.
add module author, description and license to support building
Soc Rk3399 clock driver as module.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3399.c | 55 +++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ce1d2446f142..40ff17aee5b6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -5,9 +5,11 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/module.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <dt-bindings/clock/rk3399-cru.h>
@@ -1600,3 +1602,56 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
 	rockchip_clk_of_add_provider(np, ctx);
 }
 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
+
+struct clk_rk3399_inits {
+		void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
+	.inits = rk3399_pmu_clk_init,
+};
+
+static const struct clk_rk3399_inits clk_rk3399_cru_init = {
+	.inits = rk3399_clk_init,
+};
+
+static const struct of_device_id clk_rk3399_match_table[] = {
+	{
+		.compatible = "rockchip,rk3399-cru",
+		.data = &clk_rk3399_cru_init,
+	},  {
+		.compatible = "rockchip,rk3399-pmucru",
+		.data = &clk_rk3399_pmucru_init,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
+
+static int __init clk_rk3399_probe(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match;
+	const struct clk_rk3399_inits *init_data;
+
+	match = of_match_device(clk_rk3399_match_table, &pdev->dev);
+	if (!match || !match->data)
+		return -EINVAL;
+
+	init_data = match->data;
+	if (init_data->inits)
+		init_data->inits(np);
+
+	return 0;
+}
+
+static struct platform_driver clk_rk3399_driver = {
+	.driver		= {
+		.name	= "clk-rk3399",
+		.of_match_table = clk_rk3399_match_table,
+	},
+};
+builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
+
+MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:clk-rk3399");
-- 
2.17.1




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Re: [PATCH v2 6/6] clk: rockchip: rk3399: Support module build

[Kever Yang]

On 2020/9/3 下午2:32, Elaine Zhang wrote:
> support CLK_OF_DECLARE and builtin_platform_driver_probe
> double clk init method.
> add module author, description and license to support building
> Soc Rk3399 clock driver as module.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>   drivers/clk/rockchip/clk-rk3399.c | 55 +++++++++++++++++++++++++++++++
>   1 file changed, 55 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
> index ce1d2446f142..40ff17aee5b6 100644
> --- a/drivers/clk/rockchip/clk-rk3399.c
> +++ b/drivers/clk/rockchip/clk-rk3399.c
> @@ -5,9 +5,11 @@
>    */
>   
>   #include <linux/clk-provider.h>
> +#include <linux/module.h>
>   #include <linux/io.h>
>   #include <linux/of.h>
>   #include <linux/of_address.h>
> +#include <linux/of_device.h>
>   #include <linux/platform_device.h>
>   #include <linux/regmap.h>
>   #include <dt-bindings/clock/rk3399-cru.h>
> @@ -1600,3 +1602,56 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
>   	rockchip_clk_of_add_provider(np, ctx);
>   }
>   CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
> +
> +struct clk_rk3399_inits {
> +		void (*inits)(struct device_node *np);
> +};
> +
> +static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
> +	.inits = rk3399_pmu_clk_init,
> +};
> +
> +static const struct clk_rk3399_inits clk_rk3399_cru_init = {
> +	.inits = rk3399_clk_init,
> +};
> +
> +static const struct of_device_id clk_rk3399_match_table[] = {
> +	{
> +		.compatible = "rockchip,rk3399-cru",
> +		.data = &clk_rk3399_cru_init,
> +	},  {
> +		.compatible = "rockchip,rk3399-pmucru",
> +		.data = &clk_rk3399_pmucru_init,
> +	},
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
> +
> +static int __init clk_rk3399_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	const struct of_device_id *match;
> +	const struct clk_rk3399_inits *init_data;
> +
> +	match = of_match_device(clk_rk3399_match_table, &pdev->dev);
> +	if (!match || !match->data)
> +		return -EINVAL;
> +
> +	init_data = match->data;
> +	if (init_data->inits)
> +		init_data->inits(np);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver clk_rk3399_driver = {
> +	.driver		= {
> +		.name	= "clk-rk3399",
> +		.of_match_table = clk_rk3399_match_table,
> +	},
> +};
> +builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
> +
> +MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:clk-rk3399");

This looks good to me, so

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,

- Kever




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