Re: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value

From: Inki Dae <inki.dae@samsung.com>
To: Chanho Park <chanho61.park@samsung.com>,
	'Alim Akhtar' <alim.akhtar@samsung.com>,
	'Avri Altman' <avri.altman@wdc.com>,
	"'James E . J . Bottomley'" <jejb@linux.ibm.com>,
	"'Martin K . Petersen'" <martin.petersen@oracle.com>,
	'Krzysztof Kozlowski' <krzysztof.kozlowski@canonical.com>
Cc: 'Bean Huo' <beanhuo@micron.com>,
	'Bart Van Assche' <bvanassche@acm.org>,
	'Adrian Hunter' <adrian.hunter@intel.com>,
	'Christoph Hellwig' <hch@infradead.org>,
	'Can Guo' <cang@codeaurora.org>,
	'Jaegeuk Kim' <jaegeuk@kernel.org>,
	'Gyunghoon Kwon' <goodjob.kwon@samsung.com>,
	linux-samsung-soc@vger.kernel.org, linux-scsi@vger.kernel.org,
	cpgs@samsung.com
Subject: Re: [PATCH v3 03/17] scsi: ufs: ufs-exynos: change pclk available max value
Date: Tue, 28 Sep 2021 11:18:03 +0900	[thread overview]
Message-ID: <2038148563.21632795603027.JavaMail.epsvc@epcpadp3> (raw)
In-Reply-To: <00f401d7b390$017ed1f0$047c75d0$@samsung.com>


21. 9. 27. 오후 8:08에 Chanho Park 이(가) 쓴 글:
>>>>>  #define PCLK_AVAIL_MIN	70000000
>>>>> -#define PCLK_AVAIL_MAX	133000000
>>>>> +#define PCLK_AVAIL_MAX	167000000
>>>>>
>>>>
>>>> I'm not sure but doesn't the maximum clock frequency depend on a
>>>> given machine? Is it true for all machines using different SoC?
>>>
>>> Regarding pclk(sclk_unipro)of the ufs, it can be defined by
>> mux(MUX_CLK_FSYS2_UFS_EMBD).
>>> It can be either 167MHz or 160MHz. And it can be defined by OSCCLK(26MHz)
>> as well. The value was up to 133Mhz in case of exynos7 but can be extended
>> up to 167MHz for later SoCs, AFAIK.
>>
>> Oscillator clock frequency could be different according to machine. And
>> what if UFS driver is enabled for other machine using Exynos7? Is it true
>> to use a fixed 167MHz frequency for these machines?
>> I think you could get a proper pclk frequency from device tree specific to
>> machine.
> 
> The actual pclk value will be get by CCF's clk_get_rate. PCLK_AVAIL_MAX represents the available maximum value of UFS's pclk to find an optimal value of unipro clock. I just extend the maximum pclk rate from 133MHz to 167MHz. The divider will be calculated according to the actual pclk value :)
>
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/scsi/ufs/ufs-exynos.c?h=v5.15-rc3#n287
>
Thanks for the link. I thought only PCLK_AVAIL_MAX is valid but it means available maximum clock so clock frequency between the min and max would be allowed as well. :)

Reviewed-by : Inki Dae <inki.dae@samsung.com>

Thanks,
Inki Dae

> Best Regards,
> Chanho Park
> 
>