* [PATCH v2 0/3] fixes for exynosautov9 clock
[not found] <CGME20220628104347epcas2p40f5b491f6c31b07300b5b17fe108bef7@epcas2p4.samsung.com>
@ 2022-06-28 10:41 ` Chanho Park
[not found] ` <CGME20220628104347epcas2p3cc1c9c7b17a449814fc2596f00052985@epcas2p3.samsung.com>
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Chanho Park @ 2022-06-28 10:41 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
There are some fixes for exynosautov9 such as clock id numbering,
missing clocks and register offsets.
Changes from v1:
- Add Krzysztof's R-B tags for #1 and #3 patches
- Drop fixes tag of #2 patch
Chanho Park (3):
dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
clk: samsung: exynosautov9: add missing gate clks for peric0/c1
clk: samsung: exynosautov9: correct register offsets of peric0/c1
drivers/clk/samsung/clk-exynosautov9.c | 28 ++++++----
.../dt-bindings/clock/samsung,exynosautov9.h | 56 +++++++++----------
2 files changed, 46 insertions(+), 38 deletions(-)
--
2.36.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
[not found] ` <CGME20220628104347epcas2p3cc1c9c7b17a449814fc2596f00052985@epcas2p3.samsung.com>
@ 2022-06-28 10:41 ` Chanho Park
2022-06-29 19:35 ` Chanwoo Choi
0 siblings, 1 reply; 8+ messages in thread
From: Chanho Park @ 2022-06-28 10:41 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
they should be defined correctly as numerical order.
Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
.../dt-bindings/clock/samsung,exynosautov9.h | 56 +++++++++----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index ea9f91b4eb1a..a7db6516593f 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -226,21 +226,21 @@
#define CLK_GOUT_PERIC0_IPCLK_8 28
#define CLK_GOUT_PERIC0_IPCLK_9 29
#define CLK_GOUT_PERIC0_IPCLK_10 30
-#define CLK_GOUT_PERIC0_IPCLK_11 30
-#define CLK_GOUT_PERIC0_PCLK_0 31
-#define CLK_GOUT_PERIC0_PCLK_1 32
-#define CLK_GOUT_PERIC0_PCLK_2 33
-#define CLK_GOUT_PERIC0_PCLK_3 34
-#define CLK_GOUT_PERIC0_PCLK_4 35
-#define CLK_GOUT_PERIC0_PCLK_5 36
-#define CLK_GOUT_PERIC0_PCLK_6 37
-#define CLK_GOUT_PERIC0_PCLK_7 38
-#define CLK_GOUT_PERIC0_PCLK_8 39
-#define CLK_GOUT_PERIC0_PCLK_9 40
-#define CLK_GOUT_PERIC0_PCLK_10 41
-#define CLK_GOUT_PERIC0_PCLK_11 42
+#define CLK_GOUT_PERIC0_IPCLK_11 31
+#define CLK_GOUT_PERIC0_PCLK_0 32
+#define CLK_GOUT_PERIC0_PCLK_1 33
+#define CLK_GOUT_PERIC0_PCLK_2 34
+#define CLK_GOUT_PERIC0_PCLK_3 35
+#define CLK_GOUT_PERIC0_PCLK_4 36
+#define CLK_GOUT_PERIC0_PCLK_5 37
+#define CLK_GOUT_PERIC0_PCLK_6 38
+#define CLK_GOUT_PERIC0_PCLK_7 39
+#define CLK_GOUT_PERIC0_PCLK_8 40
+#define CLK_GOUT_PERIC0_PCLK_9 41
+#define CLK_GOUT_PERIC0_PCLK_10 42
+#define CLK_GOUT_PERIC0_PCLK_11 43
-#define PERIC0_NR_CLK 43
+#define PERIC0_NR_CLK 44
/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER 1
@@ -272,21 +272,21 @@
#define CLK_GOUT_PERIC1_IPCLK_8 28
#define CLK_GOUT_PERIC1_IPCLK_9 29
#define CLK_GOUT_PERIC1_IPCLK_10 30
-#define CLK_GOUT_PERIC1_IPCLK_11 30
-#define CLK_GOUT_PERIC1_PCLK_0 31
-#define CLK_GOUT_PERIC1_PCLK_1 32
-#define CLK_GOUT_PERIC1_PCLK_2 33
-#define CLK_GOUT_PERIC1_PCLK_3 34
-#define CLK_GOUT_PERIC1_PCLK_4 35
-#define CLK_GOUT_PERIC1_PCLK_5 36
-#define CLK_GOUT_PERIC1_PCLK_6 37
-#define CLK_GOUT_PERIC1_PCLK_7 38
-#define CLK_GOUT_PERIC1_PCLK_8 39
-#define CLK_GOUT_PERIC1_PCLK_9 40
-#define CLK_GOUT_PERIC1_PCLK_10 41
-#define CLK_GOUT_PERIC1_PCLK_11 42
+#define CLK_GOUT_PERIC1_IPCLK_11 31
+#define CLK_GOUT_PERIC1_PCLK_0 32
+#define CLK_GOUT_PERIC1_PCLK_1 33
+#define CLK_GOUT_PERIC1_PCLK_2 34
+#define CLK_GOUT_PERIC1_PCLK_3 35
+#define CLK_GOUT_PERIC1_PCLK_4 36
+#define CLK_GOUT_PERIC1_PCLK_5 37
+#define CLK_GOUT_PERIC1_PCLK_6 38
+#define CLK_GOUT_PERIC1_PCLK_7 39
+#define CLK_GOUT_PERIC1_PCLK_8 40
+#define CLK_GOUT_PERIC1_PCLK_9 41
+#define CLK_GOUT_PERIC1_PCLK_10 42
+#define CLK_GOUT_PERIC1_PCLK_11 43
-#define PERIC1_NR_CLK 43
+#define PERIC1_NR_CLK 44
/* CMU_PERIS */
#define CLK_MOUT_PERIS_BUS_USER 1
--
2.36.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
[not found] ` <CGME20220628104347epcas2p4502a4524de0c98ababe8cab4b7b73c3f@epcas2p4.samsung.com>
@ 2022-06-28 10:41 ` Chanho Park
2022-06-29 9:59 ` Krzysztof Kozlowski
2022-06-29 19:36 ` Chanwoo Choi
0 siblings, 2 replies; 8+ messages in thread
From: Chanho Park @ 2022-06-28 10:41 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
"gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
and peric1 respectively.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index d9e1f8e4a7b4..c5a4e1bee711 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
+ "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
"mout_peric0_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
@@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
+ "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
"mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
--
2.36.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1
[not found] ` <CGME20220628104347epcas2p48a7fe482ad82004c145fcf90e32eaec6@epcas2p4.samsung.com>
@ 2022-06-28 10:41 ` Chanho Park
2022-06-29 19:37 ` Chanwoo Choi
0 siblings, 1 reply; 8+ messages in thread
From: Chanho Park @ 2022-06-28 10:41 UTC (permalink / raw)
To: Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk,
linux-arm-kernel, Chanho Park
Some register offsets of peric0 and peric1 cmu blocks need to be
corrected and re-ordered by numerical order.
Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/samsung/clk-exynosautov9.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index c5a4e1bee711..76c4841f2970 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -1170,9 +1170,9 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
-#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
@@ -1422,14 +1422,14 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
-#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
@@ -1467,9 +1467,9 @@ static const unsigned long peric1_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
- CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
--
2.36.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-28 10:41 ` [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
@ 2022-06-29 9:59 ` Krzysztof Kozlowski
2022-06-29 19:36 ` Chanwoo Choi
1 sibling, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 9:59 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
On 28/06/2022 12:41, Chanho Park wrote:
> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
> and peric1 respectively.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
2022-06-28 10:41 ` [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
@ 2022-06-29 19:35 ` Chanwoo Choi
0 siblings, 0 replies; 8+ messages in thread
From: Chanwoo Choi @ 2022-06-29 19:35 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
On 22. 6. 28. 19:41, Chanho Park wrote:
> There are duplicated definitions of peric0 and peric1 cmu blocks. Thus,
> they should be defined correctly as numerical order.
>
> Fixes: 680e1c8370a2 ("dt-bindings: clock: add clock binding definitions for Exynos Auto v9")
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> .../dt-bindings/clock/samsung,exynosautov9.h | 56 +++++++++----------
> 1 file changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index ea9f91b4eb1a..a7db6516593f 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -226,21 +226,21 @@
> #define CLK_GOUT_PERIC0_IPCLK_8 28
> #define CLK_GOUT_PERIC0_IPCLK_9 29
> #define CLK_GOUT_PERIC0_IPCLK_10 30
> -#define CLK_GOUT_PERIC0_IPCLK_11 30
> -#define CLK_GOUT_PERIC0_PCLK_0 31
> -#define CLK_GOUT_PERIC0_PCLK_1 32
> -#define CLK_GOUT_PERIC0_PCLK_2 33
> -#define CLK_GOUT_PERIC0_PCLK_3 34
> -#define CLK_GOUT_PERIC0_PCLK_4 35
> -#define CLK_GOUT_PERIC0_PCLK_5 36
> -#define CLK_GOUT_PERIC0_PCLK_6 37
> -#define CLK_GOUT_PERIC0_PCLK_7 38
> -#define CLK_GOUT_PERIC0_PCLK_8 39
> -#define CLK_GOUT_PERIC0_PCLK_9 40
> -#define CLK_GOUT_PERIC0_PCLK_10 41
> -#define CLK_GOUT_PERIC0_PCLK_11 42
> +#define CLK_GOUT_PERIC0_IPCLK_11 31
> +#define CLK_GOUT_PERIC0_PCLK_0 32
> +#define CLK_GOUT_PERIC0_PCLK_1 33
> +#define CLK_GOUT_PERIC0_PCLK_2 34
> +#define CLK_GOUT_PERIC0_PCLK_3 35
> +#define CLK_GOUT_PERIC0_PCLK_4 36
> +#define CLK_GOUT_PERIC0_PCLK_5 37
> +#define CLK_GOUT_PERIC0_PCLK_6 38
> +#define CLK_GOUT_PERIC0_PCLK_7 39
> +#define CLK_GOUT_PERIC0_PCLK_8 40
> +#define CLK_GOUT_PERIC0_PCLK_9 41
> +#define CLK_GOUT_PERIC0_PCLK_10 42
> +#define CLK_GOUT_PERIC0_PCLK_11 43
>
> -#define PERIC0_NR_CLK 43
> +#define PERIC0_NR_CLK 44
>
> /* CMU_PERIC1 */
> #define CLK_MOUT_PERIC1_BUS_USER 1
> @@ -272,21 +272,21 @@
> #define CLK_GOUT_PERIC1_IPCLK_8 28
> #define CLK_GOUT_PERIC1_IPCLK_9 29
> #define CLK_GOUT_PERIC1_IPCLK_10 30
> -#define CLK_GOUT_PERIC1_IPCLK_11 30
> -#define CLK_GOUT_PERIC1_PCLK_0 31
> -#define CLK_GOUT_PERIC1_PCLK_1 32
> -#define CLK_GOUT_PERIC1_PCLK_2 33
> -#define CLK_GOUT_PERIC1_PCLK_3 34
> -#define CLK_GOUT_PERIC1_PCLK_4 35
> -#define CLK_GOUT_PERIC1_PCLK_5 36
> -#define CLK_GOUT_PERIC1_PCLK_6 37
> -#define CLK_GOUT_PERIC1_PCLK_7 38
> -#define CLK_GOUT_PERIC1_PCLK_8 39
> -#define CLK_GOUT_PERIC1_PCLK_9 40
> -#define CLK_GOUT_PERIC1_PCLK_10 41
> -#define CLK_GOUT_PERIC1_PCLK_11 42
> +#define CLK_GOUT_PERIC1_IPCLK_11 31
> +#define CLK_GOUT_PERIC1_PCLK_0 32
> +#define CLK_GOUT_PERIC1_PCLK_1 33
> +#define CLK_GOUT_PERIC1_PCLK_2 34
> +#define CLK_GOUT_PERIC1_PCLK_3 35
> +#define CLK_GOUT_PERIC1_PCLK_4 36
> +#define CLK_GOUT_PERIC1_PCLK_5 37
> +#define CLK_GOUT_PERIC1_PCLK_6 38
> +#define CLK_GOUT_PERIC1_PCLK_7 39
> +#define CLK_GOUT_PERIC1_PCLK_8 40
> +#define CLK_GOUT_PERIC1_PCLK_9 41
> +#define CLK_GOUT_PERIC1_PCLK_10 42
> +#define CLK_GOUT_PERIC1_PCLK_11 43
>
> -#define PERIC1_NR_CLK 43
> +#define PERIC1_NR_CLK 44
>
> /* CMU_PERIS */
> #define CLK_MOUT_PERIS_BUS_USER 1
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1
2022-06-28 10:41 ` [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
2022-06-29 9:59 ` Krzysztof Kozlowski
@ 2022-06-29 19:36 ` Chanwoo Choi
1 sibling, 0 replies; 8+ messages in thread
From: Chanwoo Choi @ 2022-06-29 19:36 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
On 22. 6. 28. 19:41, Chanho Park wrote:
> "gout_peric0_pclk_1" and "gout_peric1_pclk_1" should be added to peric0
> and peric1 respectively.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index d9e1f8e4a7b4..c5a4e1bee711 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1330,6 +1330,10 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
> "mout_peric0_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
> 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PCLK_1, "gout_peric0_pclk_1",
> + "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
> + 21, 0, 0),
> GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
> "mout_peric0_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
> @@ -1581,6 +1585,10 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> "mout_peric1_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0,
> 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PCLK_1, "gout_peric1_pclk_1",
> + "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
> + 21, 0, 0),
> GATE(CLK_GOUT_PERIC1_PCLK_2, "gout_peric1_pclk_2",
> "mout_peric1_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1
2022-06-28 10:41 ` [PATCH v2 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
@ 2022-06-29 19:37 ` Chanwoo Choi
0 siblings, 0 replies; 8+ messages in thread
From: Chanwoo Choi @ 2022-06-29 19:37 UTC (permalink / raw)
To: Chanho Park, Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi,
Krzysztof Kozlowski, Stephen Boyd, Michael Turquette,
Rob Herring, Krzysztof Kozlowski
Cc: Alim Akhtar, linux-samsung-soc, devicetree, linux-clk, linux-arm-kernel
On 22. 6. 28. 19:41, Chanho Park wrote:
> Some register offsets of peric0 and peric1 cmu blocks need to be
> corrected and re-ordered by numerical order.
>
> Fixes: f2dd366992d0 ("clk: samsung: exynosautov9: add cmu_peric0 clock support")
> Fixes: b35f27fe73d8 ("clk: samsung: exynosautov9: add cmu_peric1 clock support")
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index c5a4e1bee711..76c4841f2970 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1170,9 +1170,9 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
> -#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
> #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
> @@ -1422,14 +1422,14 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
> #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
> #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
> #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2058
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x205c
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x2060
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x206c
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2064
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2068
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2070
> -#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
> #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
> #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
>
> @@ -1467,9 +1467,9 @@ static const unsigned long peric1_clk_regs[] __initconst = {
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
> - CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9,
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10,
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks for fixup.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-29 19:37 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
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2022-06-28 10:41 ` [PATCH v2 0/3] fixes for exynosautov9 clock Chanho Park
[not found] ` <CGME20220628104347epcas2p3cc1c9c7b17a449814fc2596f00052985@epcas2p3.samsung.com>
2022-06-28 10:41 ` [PATCH v2 1/3] dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 Chanho Park
2022-06-29 19:35 ` Chanwoo Choi
[not found] ` <CGME20220628104347epcas2p4502a4524de0c98ababe8cab4b7b73c3f@epcas2p4.samsung.com>
2022-06-28 10:41 ` [PATCH v2 2/3] clk: samsung: exynosautov9: add missing gate clks for peric0/c1 Chanho Park
2022-06-29 9:59 ` Krzysztof Kozlowski
2022-06-29 19:36 ` Chanwoo Choi
[not found] ` <CGME20220628104347epcas2p48a7fe482ad82004c145fcf90e32eaec6@epcas2p4.samsung.com>
2022-06-28 10:41 ` [PATCH v2 3/3] clk: samsung: exynosautov9: correct register offsets of peric0/c1 Chanho Park
2022-06-29 19:37 ` Chanwoo Choi
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